A simulation and diagnosis system incorporating various time delay models and functional elements

Abstract

The application of digital simulation to all phases of digital network design is considered here as oppossed [sic] to development of simulation for one or two restricted parts of the digital process. For this reason a simulator is presented which can be consistent by varying the level of expression from the simulation of architectural structures to such detailed simulation requirements as race analysis of asynchronous sequential circuits. In order to make system simulation more than just an idea, it must be capable of handling large circuits in reasonable times. It is demonstrated that functional simulation has the potential to increase simulation speed while reducing the required storage. This potential is realized with the following features of this simulator structure: 1) a modular structure for specification and execution, 2) the capability of being easily interfaced with gate level simulation, 3) the capability of utilizing the highest level of expression for simulation, 4) a variable level of expression, 5) a relatively unrestricted type of logic that can be simulated, 6) the capabilities of using standard functional modules, 7) a fairly universal means of expressing functional modules and, 8) the use of data and control signals to further force selective trace capabilities on a module level. Greater gate level simulation capabilities are obtained by extending the basic simulator to perform the simulation of undefined signal values and the simulation of ambiguities in signal propagation speeds. The simulator presented here is part of a Test Generation and Simulation System. This system includes preprocessing, combinational test generation, automatic fault insertion as well as simulation --Abstract, page ii

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