System level ESD tests can only be performed after hardware is available. Simulating the ESD coupling into a circuit allows at least parametric and quantitative studies of the expected ESD behavior. A complete simulation requires us to model the ESD generator, the passive elements of the DUT and the response of the ICs to injected noise. Having the ultimate objective of combining IC soft error response models with the DUT structure and the ESD generator we report on progresses in modeling the ESD generator and its coupling. The model improves the useful frequency range from a few hundred MHz to about 3 GHz
