Tecnológico Nacional de México / Instituto Tecnológico de Celaya
Abstract
This paper describes the implementation of an interferogram decoding system based on a Nios II embedded microprocessor. The interferograms are obtained by using the classical Michelson Interferometer configured as the four step phase shifting profiler. This work includes the phase unwrapping solution implemented with the minimum norm method and the SoPC architecture developed with C and Verilog languages. The processing system was successfully implemented on the Nios II in a Cyclone IV FPGA. We found that the system needs an application specific hardware accelerator to improve its performance, but regardless this drawback, its capacity to unwrap is similar to other state of the art techniques
