SCALABLE FRAMEWORK WITH IDENTICAL MEMORY DIES TO ACHIEVE HIGH-CLOCK FREQUENCY

Abstract

Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture according to low latency logarithmic interconnects, which enables stacking of multiple identical memory dies (MDs), supports multiple outstanding transactions, and achieves high clock frequencies because of its highly pipelined nature. We implemented our design with STMicroelectronics CMOS-28-nm low-power technology and acquired time frequency of 500 MHz, as much as eight stacked dies (4 MB) having a memory density loss. Large needed size, and ability to tolerate latency and variations in memory access time make L2 memory a appropriate choice for 3-D integration. Within this paper, we present a synthesizable 3-D-stacking L2 memory IP component, which may be mounted on a cluster-based multicore platform through its network-on-nick interfaces offering high-bandwidth memory access with low average latency. Benchmark simulation results show adding 3-D-NUMA to some multicluster system can result in a typical performance boost of 34%. In addition, experiments and estimations make sure 3-D-NUMA is energy and power efficient, temperature friendly, and it has improvements appropriate for low-cost manufacturing. Finally, improvement is quite possible in 3-D-NUMA in contrast to its 2-D counterparts, while using condition from the art through-plastic-via technologies