International Journal of Innovative Technology and Research
Abstract
The primary challenge is the fact that individual’s codes should minimize the delay and area penalty. One of the codes which have been considered for memory protection is Reed-Solomon (RS) codes. This limits using ECCs in high-speed recollections. It has brought to using simple codes for example single error correction double error recognition (SEC-DED) codes. However, as technology scales multiple cell upsets (MCUs) be common and limit using SEC-DED codes unless of course they're coupled with interleaving. To prevent data corruption, error correction codes (ECCs) are broadly accustomed to safeguard recollections. ECCs introduce a delay penalty in being able to access the information as encoding or deciphering needs to be carried out. An identical issue happens in some kinds of recollections like DRAM which are typically arranged in modules made up of several products. In individual’s modules, the security against a tool failure instead of isolated bit errors can also be desirable. In individual’s cases, one option is by using more complex ECCs that may correct multiple bit errors. These codes derive from non-binary symbols and for that reason can correct multiple bit errors. Within this paper, single symbol error correction codes according to Reed-Solomon codes that may be implemented with low delay are suggested and evaluated. The outcomes show that they'll be implemented having a substantially lower delay than traditional single error correction RS codes
