DESIGN OF 754 IEEE BY THE MULTIPLIER OF FLOATING POINT

Abstract

In the computation of the data processing signal in the environment of the digitized phenomena plays a crucial role in its application include the multiplication of the floating point under the computation of the scientific research oriented strategy respectively. In terms of the computational strategy multiplications plays a crucial role in its implication of the operation of the arithmetic scenario. Here the implementation of the multiplier with the high precision of the floating point value of improvement in the speed relative to the FPGA vertex 6. And under the further research strategy there is an integration of the 754 IEEE standard plays a crucial role I the applicability by the order of design and flow handling under the conditionality of the different multiple expectation respectively. Here there is an improvement in the performance and also the storage capabilities by the present method in a well efficient way. Simulations have been conducted on the present method where it completely overcome the drawbacks of the several previous methods in a well oriented fashion respectively