Algorithmic tools for graphs of small treewidth are used to address questions
in complexity theory. For both arithmetic and Boolean circuits, it is shown
that any circuit of size nO(1) and treewidth O(login) can be
simulated by a circuit of width O(logi+1n) and size nc, where c=O(1), if i=0, and c=O(loglogn) otherwise. For our main construction,
we prove that multiplicatively disjoint arithmetic circuits of size nO(1)
and treewidth k can be simulated by bounded fan-in arithmetic formulas of
depth O(k2logn). From this we derive the analogous statement for
syntactically multilinear arithmetic circuits, which strengthens a theorem of
Mahajan and Rao. As another application, we derive that constant width
arithmetic circuits of size nO(1) can be balanced to depth O(logn),
provided certain restrictions are made on the use of iterated multiplication.
Also from our main construction, we derive that Boolean bounded fan-in circuits
of size nO(1) and treewidth k can be simulated by bounded fan-in
formulas of depth O(k2logn). This strengthens in the non-uniform setting
the known inclusion that SC0⊆NC1. Finally, we apply our
construction to show that {\sc reachability} for directed graphs of bounded
treewidth is in LogDCFL