Interstitial oxygen concentration role in the DW-Locos CMOS technology

Abstract

The dependence on the silicon substrate interstitial oxygen concentration of CMOS device performance using the recently developed DW-LOCOS isolation scheme is evaluated. Electrical characterisation in terms of both effective carrier generation lifetime in MOS structures and leakage current density in diodes is studied. It is shown that for the DW-LOCOS CMOS process, a noticeable reduction of the measured differences with respect to a classical wet LOCOS CMOS process flow are obtained. An improvement of the gate oxide reliability in terms of charge to breakdown is also confirmed