Mestrado em Engenharia Electrónica e TelecomunicaçõesThe advancements and dissemination of telecommunication technologies
has caused them to be employed more and more in our day-to-day life.
Recently, these technologies have been applied to vehicles, as a way of not
only improving driving safety but also the drivers' and passengers' comfort.
If vehicular communications are to become a reality, communication standards
must be created in order to allow the development of compatible
communication platforms, while also serving as a basys for application development.
The standards IEEE WAVE, alongside the IEEE 802.11p amendment,
were proposed in order to meet these demands and address some of
the speci c issues with vehicular networks, such as short connectivity times
and the highly dynamic nature of the propagation environment.
This thesis ts within the HEADWAY project, the goal of which is the creation
of a device that will perform communication between vehicles. In order
to incorporate every layer of the WAVE (Wireless Access in Vehicular Environments)
protocol stack, a development platform was conceived that will
enable the creation of a standardized communications system for vehicles.
The development platform created features an antenna, RF modules, DAC
and ADC circuits, an FPGA, a general purpose microprocessor and a GPS
module. This work is focused in the development and implementation in
FPGA of a MAC layer in accordance with the WAVE standards.
The MAC layer's di erent functionalities were divided according to their
complexity and execution time, causing our MAC's division in Upper MAC
(UMAC) and Lower MAC (LMAC). The UMAC will be implemented in
software (C) running in an FPGA embedded microprocessor and will contain
the MAC's functions that are more complex, algorithmically speaking,
but are not required to be excuted in a very short time interval, such as
frame processing and decoding. The LMAC will be implemented by VHDL
modeled hardware logic and will perform time critical functions, such as
the timestamping of received frames, and complex calculations that bene t
from the paralelism o ered by hardware logic, such as CRC computation
and error checking.
This MAC layer was implemented in an FPGA and its mechanisms were
validated
