Kourfali, Alexandra

Stroobandt, Dirk

English

Ghent University Academic Bibliography

Towards Efficient Hardware Debugging usingParameterized FPGA ReconfigurationAlexandra Kourfali and Dirk StroobandtDepartment of Electronics and Information Systems (ELIS), Ghent UniversityiGent, Technologiepark-Zwijnaarde 15, 9052 Ghent, Belgium.{Alexandra.Kourfali, Dirk Stroobandt}@UGent.beA. IntroductionEnsuring a design’s functional correctness within time-to-market constraints, continues to stand as one of the biggestchallenges for today’s ASIC design teams. Lately, circuitdesigners have turned to Field-Programmable Gate Arrays(FPGAs) for the simulation of their complete systems (FPGAemulation), that offer operating frequencies that are several or-ders of magnitude faster than simulation. However, debuggingthrough FPGA emulation has its own challenges, such as lackof on-chip signal observability. Moreover, observing a newsubset of signals requires recompilation of the circuit. Eachinstrument-compile-debug iteration can take multiple hours.B. Parameterised debugging flowWe propose a low overhead debugging flow, which is en-tirely automated and integrated within the normal FPGA CADflow. It offers debug acceleration and enhanced internal signalvisibility by using parameterised configurations (PConf). Thiswill allow us to implement parameterised hardware systems,with parameters that define different circuit instances that canbe optimised on the fly by reconfiguring for a current set ofparameter values. Our proposed debugging flow follows thetypical stages of the FPGA CAD flow and consists of twophases: the offline and the online phase.During the offline phase a generalised configuration iscreated. The circuit is fully compiled, the mapping is fixed andthe extra instrumentation is added. This allows all availablesignals to be connected with trace-buffer IP. In more detail,during the first stage, Signal Parameterisation, all signals thatcan be used for debugging are automatically selected andparameterised. These signals are annotated as parameters, asthey will change (but less frequently than the other signals)depending on the set of signals that will be traced duringdebugging. These parameters can hence be implemented inthe reconfiguration resources.1After the extra instrumentation has been added, the designis synthesised and then, during technology mapping (TCON-Map), the parameterized network (generated during synthesis),is not directly mapped onto the resource primitives availablein the target FPGA architecture, but intermediately on abstractprimitives that introduce and allow the reconfigurability ofthe logic and routing resources. Finally, the Place & Route1We assume that the higher utilization of routing resources does not affectthe placement of the design.(TPaR) stage can enable routing of the circuit where itsrouting resources can be reused during the fault emulationand this drastically reduces the area usage. At the end of thecomputationally intensive compile phase, a virtual intermediateFPGA configuration is created.During the online phase, for every debugging cycle thenetwork is partially reconfigured with the exact signals thedesigner wishes to trace at that specific instance. Here, only theconfiguration cells of all the routing switch boxes and the con-nection boxes for the memory resources will be reprogrammed,instead of the full recompilation and/or reconfiguration, as it isthe case in related work. This online step will be future work,as we first focus on the offline part of the toolflow.C. Preliminary resultsIn order to evaluate our proposed method, we are integrat-ing our techniques inside VTR, so that it can be complient withour parameterised debugging infrastructure. The first experi-ments with the VTR benchmarks indicate that we only needthe area for the largest circuit instance implementation, insteadof the sum of areas of the initial and the added implementation.This enables us to include debugging infrastructure withoutarea overhead.Our technique reduces the critical path delay of the addedfunctionality for the faults by reducing the number of LUTsand the routing infrastructure on the critical path. The logicdepth (inversely related to clock speed) of the design did notchange by adding the extra debugging infrastructure.The runtime overhead depends on the number of times theemulator needs to be reconfigured and on the time to evaluatethe PConf and to reconfigure the bits that changed. The timeoverhead can be expressed as the single specialization time(for specializing the FPGA once) multiplied by the number oftimes a new signal set will be activated. The evaluation timeis used to evaluate the Boolean functions in the parameterizedconfiguration produced by the offline generic stage of theTCON tool flow (maximum 50 µs). Thus, each parameterisedconfiguration can be 3 orders of magnitude faster than a fullreconfiguration (176 milliseconds for a Xilinx Virtex-5 FPGA).D. ConclusionA low overhead debugging method is proposed. The main(parameterised) debugging infrastructure is presented, which ismeant for both emulation approaches (for ASIC verification)and on-line in field debugging approaches (for FPGA designverification) and it includes increasing design observability.This infrastructure lies within the circuit implementation andis only invoked when a debugging parameter is set. Therefore,this infrastructure is always present but does not require muchadditional area. The area needed is found by introducingparameterized reconfiguration in the application. Hence, thanksto the fact that there is virtually no overhead over the originalimplementation, we can add the debugging functionality forfree.

Towards efficient hardware debugging using parameterized FPGA reconfiguration

https://biblio.ugent.be/publication/8583690/file/8583691.pdf

Towards efficient hardware debugging using parameterized FPGA reconfiguration

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