The paper proposes a compact but accurate electro-thermal model of a long on-chip interconnect embedded in a ULSI circuit. The model is well suited to be interfaced with the commercially available tools employed in ICs design for interconnect parasitic extraction

Codecasa, L.

D'Amore, D.

Maffezzoni, P.

Spennagallo, N.

SPENNAGALLO, NADIA

CODECASA, LORENZO

D'AMORE, DARIO

MAFFEZZONI, PAOLO

Archivio istituzionale della ricerca - Politecnico di Milano

Lumped Electro-Thermal Model of on-Chip Interconnects

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Lumped Electro-Thermal Model of On-chip
Interconnects
Nadia Spennagallo, Lorenzo Codecasa, Dario D’Amore, and Paolo Maffezzoni
Politecnico di Milano
Dipartimento di Elettronica e Informazione
P.zza Leonardo Da Vinci 32, I-20133 Milano, Italy.
Email: (spennagallo, codecasa, damore, pmaffezz)@elet.polimi.it
Abstract— The paper proposes a compact but accurate electro-
thermal model of a long on-chip interconnect embedded in a
ULSI circuit. The model is well suited to be interfaced with
the commercially available tools employed in ICs design for
interconnect parasitic extraction.
I. INTRODUCTION
In modern nanometer ULSI circuits interconnects play a
dominant role in determining the timing behavior of the digital
systems [1]. The verification of system performance and the
analysis of signal integrity need the employment of specific
simulation tools for the extraction of interconnect parasitics
and thus for the estimation of interconnect propagation delay
[2], [3].
Simultaneously the aggressive scaling down of devices dimen-
sion and the increase of operating frequency has dramatically
magnified the electrical power density leading to a signifi-
cant temperature increase in the substrate and in the metal
interconnects. The increase of temperature determines, among
other effects, an increase of electrical resistivity of metal inter-
connect and thus a degradation of propagation delay. In high-
performance digital systems the nonuniform nature of power
dissipation and of boundary conditions imposed by packaging
and cooling mechanism can be such that relevant temperature
gradients appear on the substrate [4]. In this condition, the
thermally-induced degradation of a long interconnect depends
on the path followed by the line over the substrate.
Recently a method for the analysis of nonuniform substrate
thermal effects in ULSI interconnects has been presented [5].
The proposed method follows an analytical approach and em-
ploys a one dimensional distributed model of the interconnect
and closed form expressions of substrate temperature profiles
as interconnect boundary conditions. The analytical method is
suited to explore the qualitative shape of temperature profile
in the interconnect but is not suited to be interfaced with the
tools that are commonly employed in ICs design. Parasitic
extractor tools in fact model interconnections by discretizing
them in a set of elementary subsections and thus they supply
lumped RC models [3]. In addition, the layout of ULSI circuits
is very complicated and a reliable thermal analysis can be
accomplished only numerically; as a consequence temperature
profile over the chip substrate is available only in a set of
discrete points.
To cope with these aspects, in this work we propose an
alternative approach to electro-thermal analysis of long ULSI
interconnects that is able to handle as an input the RC
lumped model supplied by extraction tools. The proposed
method exploits an interconnect lumped electro-thermal model
that employs as boundary condition the substrate temperature
profile derived by a numerical thermal analysis (or alterna-
tively through on chip measurements). The compact model
allows the designer to evaluate the temperature increase in
the interconnect and the effective propagation delay as a
function of interconnect path over the substrate. It is shown
that in high-performance processors interconnect layouts that
are equivalent from a purely electrical point of view can
have significantly different propagation delay due to thermally-
induced degradation.
II. BACKGROUND: INTERCONNECT ELECTRICAL MODEL
FOR TIMING ANALYSIS
We start with by considering an on-chip interconnection
embedded in a ULSI layout, Fig. 1 shows the typical shape
of such an interconnect.
METAL
w
t
t m
ox
x∆
SUBSTRATE
OXIDE
Fig. 1. Interconnect line
The common approach to on-chip interconnection analysis
is done by determining the parasitic elements associated to
the net and thus building up an equivalent purely electrical
model. In commercially available extraction tools, this is
accomplished through the following steps: a) the interconnect
is first fractured in subsections accordingly to internal rules
(such as the presence of crossing nets or at line corners); b)
for each subsection the electrical resistance and the parasitic
capacitance is computed. As a result a ladder RC electrical
model of the interconnect is deduced where CEk and R0Ek
are the parasitic capacitance and the electrical resistance
respectively of the k-th section, see Fig. 2. It is worthwhile
observing here that the R0Ek electrical resistance associated to
the section is determined by considering the resistivity of metal
at a reference temperature and that the variation of such value
due the increase of temperature and to temperature gradient
is commonly not considered. The purely electrical model is
further employed in the timing analysis of electrical system
to estimate the time delay introduced by the interconnect. To
such a purpose we consider here a line connected to an input
driver with on-resistance Rdr and junction capacitance Cdr
and terminated by a load capacitance CL. The delay D for
signal propagation through the line can be written using the
distributed RC Elmore delay model
D = Rdr
(
n∑
i=1
CEi + CL
)
+
n∑
i=1
REi

 n∑
j=i
CEj + CL


(1)
where CEi and REi are the capacitances and resistances
evaluated by the extraction tool for each elementary section
[6].
RENREk
CEk CENCE1
RE1
CL
Fig. 2. Electrical RC model of the interconnect line
III. ELECTRO-THERMAL ANALYSIS
The on-chip interconnect is embedded into the complex
geometry of the chip layout so that the temperature distri-
bution along interconnect is the result of two different heating
mechanisms: a) the mutual heating of active devices integrated
over the chip substrate; b) the interconnect self heating due
to Joule effect. The chip layout is described by placing and
connecting over the substrate a set of standard elementary
circuit layout, referred to as standard cells. From the circuit
layout we know the location of each standard cell and the
average dissipated electrical power. From this information we
first determine the steady-state temperature distribution over
the whole substrate. To such a purpose we formulate the dis-
cretized heat equation into the geometry of the chip substrate
and determine an equivalent thermal network by following
the well known approach. The substrate is discretized with
a finite difference grid into elementary volumes and for each
volume a node into the thermal network is introduced. Each
node is connected to all the the nodes of the neighborhood
volumes through the thermal resistance that accounts for the
heat diffusion mechanism. The thermal exchange between the
chip and external environment is described through external
thermal resistors that are deduced from the boundary exchange
conditions. Note that we are interested only in steady-state
DC temperature profile and thus dynamic thermal capacitors
are not considered. The average power dissipated by each
cell is injected as an equivalent (current) source into the
thermal node corresponding to the standard cell volume. We
remark that generally, due to the huge number of standard cells
that form a layout, each elementary volume of the thermal
discretization contains many standard cells volumes. In this
case the standard cells are grouped together to form a single
equivalent source and their average powers are accumulated.
The steady-state solution of substrate temperature allows to
compute the temperature distribution in the substrate along the
path that is obtained projecting the interconnect geometry over
the substrate. This substrate temperature distribution along
the line path becomes the boundary condition to use when
analyzing the self heating into the interconnect.
We concentrate now on the electro-thermal model of the
interconnect. To derive the interconnect electro-thermal model
we consider the interconnect line (Fig. 1), of length L, width
w running over the substrate surface at a distance tox and
connected to the substrate through vias at its two ends.
As said before the interconnection line is partitioned in ele-
mentary sections from the parasitic extractor tool that supplies
an RC electrical model.
Digital circuits operate at very high frequency and electrical
time constants are several order of magnitudes smaller than
thermal ones. Thus in order to determine the steady-state
temperature profile we limit to consider the average power
dissipated by each line section. Calling Irms, the root mean
square amplitude of the current that flows in the line, we
assume that the root mean square current is constant in all
sections. The electrical power dissipated in the k-th section
of the interconnect is thus given by:
Pk = REkI
2
rms (2)
On the other hand the local electrical resistance REk , depends
on the local temperature of the interconnect section as follows:
REk = R
0
Ek
(1 + β · (Tlinek − T0)) (3)
where R0Ek is the electrical resistance supplied by the parasitic
extraction tool and computed at reference temperature T0, β
is the temperature coefficient of electrical resistivity [1/◦C],
and Tlinek is the temperature of the k-th elementary section;
Tk = Tlinek − T0 is the temperature increase over reference
temperature.
Therefore, power dissipation can be rewritten as follows:
PEk = R
0
Ek
(1+β ·Tk) ·I
2
rms = R
0
Ek
·I2rms +R
0
Ek
·β ·Tk ·I
2
rms
(4)
The power effectively dissipated by each section is composed
of two contributions the first of which depends only on the
effective value of current flowing into the line while the
second one depends in turn on the increase of temperature in
the interconnect section. The compact electro-thermal model
of the interconnect is presented in Fig. 3. The electrically
dissipated power is injected into the thermal nodes through
two current sources, the first one is an independent current
source of value R0Ek · I
2
rms, the second one is a temperature-
controlled current source of value R0Ek · β · Tk · I
2
rms. Heat
kT
Ek
0R Tk Irms
2βREk
0
I
rms
2
RTox k
Tsub k
RTm k
Tsub 1
Rvia
Tsub n
Rvia
Fig. 3. Interconnect electro-thermal model
diffusion into the line is described by thermal resistors RTmk
RTmk =
1
km
∆xk
w tm
(5)
where km is the metal thermal conductivity and ∆xk is the
length of k-th interconnect section.
Heat exchange toward the underneath substrate is modeled
through an equivalent resistor RToxk and an equivalent tem-
perature source imposing the local substrate temperature Tsubk
determined by the previously described substrate thermal
analysis. For what concerns the oxide thermal resistance it
can be written as follows:
RToxk =
1
k∗ox
tox
w ∆xk
(6)
where k∗ox is the effective oxide thermal conductivity and tox
is the oxide thickness.
The effective oxide thermal conductivity k∗ox is a shape-
dependent parameter which considers the geometrical
configuration of the heat conducting body on the thermal
conductivity.
For the case of a rectangular shape parallel to an infinite
plate with dimension that satisfy the condition w/tox > 0.4
we use a Bilotti’s estimation [7], in the other case, when this
condition is not satisfied (like the geometrical configuration
of the interconnect in deep submicron technologies) we use
a more accurate expression for k∗ox introduced by Andrews [8]:
k∗ox = kox ·
tox
w
· 1.685 ·
[
log
(
1 +
tox
w
)]
−0.59
·
(
tox
tm
)
−0.078
(7)
At the two ends of the interconnect there are two vias that
connected the line to the substrate. The thermal resistance of
the vias are calculated as follows:
Rvia =
1
km
tox
w ∆x
(8)
For a given chip and interconnect layouts, the solution of
electro-thermal model allows to determine the temperature
increase in each section of the interconnection and thus from
(1) to deduce the following thermal-aware delay propagation
D = Rdr
(
n∑
i=1
CEi + CL
)
+ (9)
n∑
i=1
(R0Ei + R
0
Ei
β Ti)

 n∑
j=i
CEj + CL

 (10)
where CEi and REi are the capacitances
IV. NUMERICAL RESULTS
We consider an high-performance microprocessor manufac-
tured in 150 nm HCMOS technology and integrated in the
frame of a ULSI chip. The layout of the sole microprocessor
is composed of about 200,000 transistors and is described
by about 20,000 standard cells; the microprocessor occupies
a chip area of of 0.216 mm2 (dimensions 0.47 mm x
0.46 mm) that is referred to as active area in Fig. 4. The
average power dissipated, the geometry and the coordinates
of each cell forming the microprocessor is available from the
layout description language and is thus an input data. The
microprocessor on the whole dissipates an electrical power of
0.9 W that is distributed in a nonuniform way over the active
area being significantly greater near the bottom-right corner.
The microprocessor is placed over a silicon die of thickness
100 µm.
First we compute the temperature distribution over the sub-
strate by considering a simulation domain of 1.27 mm x
1.26 mm containing the microprocessor and we impose
adiabatic condition on the later walls of the domain and a
uniform heat exchange coefficient h=10000 W/m2 on the
bottom face of the domain. Fig. 4 shows the computed steady-
state temperature distribution over the chip substrate; you see
that the maximum temperature of 83 ◦C is reached near the
bottom-right side of the active area and that a gradient of 36 ◦C
establishes on the chip.
After that we take two different interconnect lines belonging
to the first Metal layer and connecting points A an B over the
chip through two different paths path-I and path-II . Fig. 5
reports the computed temperature profiles over the substrate
along Path-I and Path-II. Note that the temperature gradient
along Path-I (about 30 ◦C) is much larger than the one along
Path-II.
The two lines have the same geometry, they have length
L = 993µm, width w = 0.4µm and thickness tm = 0.55µm
and are placed at a distance tox = 1.33µm over the substrate.
The two lines are drawn in the layout according to the
electrical design rules and from a purely electrical point of
view they are absolutely equivalent. As we are going to
show they are not equivalent when thermal effects are taken
into account. The IC extractor tool supplies a ladder RC
interconnect models formed of many cells corresponding to
a total electrical resistance of 122 Ω and a total parasitic
capacitance of 91.9 fF . The two lines drive a load capacitance
CL = 40 fF . We employ such RC models and the numerically-
computed temperature map to form the compact electro-
thermal interconnects models as described in section 3. Then
we assume a root mean square interconnect current Irms =
5 mA and we employ the compact electro-thermal model to
estimate the temperature profiles along the interconnects. The
electro-thermal model is formed of 55 sections. Fig. 6 shows
the temperature into the interconnects. From the interconnect
temperature we determine the interconnect resistances as mod-
ified by heating effect and then we deduce the thermal-aware
propagation delay according to RC Elmore delay model (9).
−4 −2 0 2 4 6 8
x 10−4
−4
−2
0
2
4
6
8
x 10−4 die, active area, paths, level curves of sustrate temperature
x axis
y 
ax
is
50°C
55°C
60°C
65°C
82°C
80°C
70°C
path I 
path II 
active area
A
B
Fig. 4. Chip domain and path I and path II from point A to point B on a
substrate with temperature distribution
0 10 20 30 40 50 6050
55
60
65
70
75
80
85
substrate temperature distribution along the two paths
sections of the line
te
m
pe
ra
tu
re
 [°
C]
path I
path II
Fig. 5. Substrate temperature profile along the interconnects paths
Fig. 7 reports the estimated delay along the two different
paths for the cases: a) employing the compact electro-thermal
model; b) considering a constant temperature T0 = 27 ◦C.
The total propagation delay from point A to point B esti-
mated through a purely electrical analysis at T0 temperature
is D0 = 10.5·10−12 s. While when the electro-thermal effect
is considered the total delays are D1 = 12.14 ·10−12 s and D2
= 12.76 ·10−12 s for the cases of path I and path II (hottest
path) respectively. Neglecting heating effect leads thus to
underestimate the propagation delay of about 22% with respect
the effective delay. The degradation induced by heating effect
is relevant and can not be disregarded in the design phase.
When thermal effects are considered we see that the difference
0 10 20 30 40 50 6050
55
60
65
70
75
80
85
metal temperature distribution along the two lines
sections of the line
te
m
pe
ra
tu
re
 [°
C]
path I
path II
Fig. 6. Temperature profile along the interconnects
between the delay along path-I and path-II corresponds to ∆D
= 6.1 ·10−13 sec and to a relative difference of about 5%. This
information results to be important to optimize interconnect
placement in order to minimize skew effect.
0 10 20 30 40 50 600
0.2
0.4
0.6
0.8
1
1.2
1.4 x 10
−11
L = 993 um;  dx = 18 um
D
el
ay
Delays in the two different paths
Tm=55°C  D=1.2148e−11
Tm=68°C  D=1.2757e−11
path II path I
at the reference temperature
Fig. 7. Delay profile along the interconnects lines end along the line at the
reference temperature
V. CONCLUSION
The paper presents a numerical approach to compute the
temperature profile in long ULSI interconnects accounting for
both mutual effect induced by active devices and self heating
due to Joule effect. The method uses the interconnect lumped
model extracted by ICs design tools and the numerically com-
puted substrate temperature map as determined by a numerical
thermal analysis. The model is compact in that it accounts
for electro-thermal feedback mechanism through equivalent
sources. For a given chip layout and interconnect path over the
substrate the proposed model allows the designer to evaluate
the temperature increase in the line and the propagation delay.
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Lumped electro-thermal model of on-chip interconnects

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Lumped electro-thermal model of on-chip interconnects

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Archivio istituzionale della ricerca - Politecnico di Milano

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