A Multi-Core Basic Software as Key Enabler of Application Software Distribution

Abstract

International audienceIn the last 20 years, functional evolution in the automotive Powertrain has been motivated by three main pillars: low CO2 emissions (synonym to low fuel consumption), low emissions (particles, NOx, Co, HC), increase of torque throughput.In addition to these permanent objectives (e.g. Euro 4 ... Euro7 standard), new constraints are rising up now, like integrated transmission systems, electrification, autonomous driving, connectivity, etc...Finally, new complexities have to be handled, and high-end system is not anymore synonym of high cylinder number. Such system requires today 6 times as much computation power as 15 years ago, when 32 bits controllers (MPC 563 @ 40MHz) were introduced. Similarly, we estimate the needed computation power in 2022 to be twice compared to today.Such need cannot be reached anymore by increasing frequency (from 40Mhz in 2003 to 300MHz today) and reducing silicon structures (from 130 to 40 nm), but only by multicore computing.Nevertheless, multicore architecture does not provide automatically a gain of performance, particularly for highly coupled systems with high connexion with the HW, and hard real-time requirements. It might even be counter-productive, if not properly handled.The challenge of sharing memory cross cores in an efficient way has already been presented in a previous ERTS2 edition. We want now to elaborate on the importance of a well prepared basic software.A classical embedded SW (as defined by AR, too) is split in parts:The high level applicative SW (ASW) must be architectured in a way, that it can be easily reused cross platforms, and project configurations (4, 6 cylinders, gasoline, diesel, ...).Its reusability cross different HW platforms is ensured by the basic software (BSW), that gives access to the peripherals abstracting different HW controllers & ASIC families (different suppliers, from 1 to 6 cores, ...).In this contribution, we will elaborate on the main BSW principles that allowed us to efficiently use the performances of the new multicore controller. In addition to efficiency, a maximum freedom in the allocation of the ASW Runnables is required, knowing that many of them need an access to the HW peripherals. Of course, locking other cores while accessing the peripheral is not an option, like enforcing all ASW components with HW interface to be integrated on one same core.We will explain how the BSW itself is distributed, and how the access to the peripherals from different cores is made possible. We will explain the paradigms used in the design of the BSW, as well as the main cross core communication principles. Furthermore, we will describe a concept of core abstraction, allowing to share even the same task architecture between projects based on different controllers.Finally, we will propose a qualification of the BSW into 3 multicore conformance classes. In the highest level (MCC3), the ASW can be freely integrated in so called System Events, independently of any core consideration