A. FACEN

A.BONI

AZZOLINI C.

D. VECCHI

M.PARENTI

The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented

AZZOLINI, Cristiano

BONI, Andrea

M. PARENTI

Archivio istituzionale della Ricerca -  Università degli Studi di Parma

Design of a 2-GS/s 8-b Self-Calibrating ADC in 0.18-um CMOS Technology

Design og a 2-GS/s 8-b Self-Calibrating ADC in 0.18-um CMOS Technology

Design og a 2-GS/s 8-b Self-Calibrating ADC in 0.18-um CMOS Technology

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Archivio istituzionale della Ricerca - Università degli Studi di Parma