The optimum decoding of component codes in block coded modulation (BCM) schemes requires the use of the log-likelihood ratio (LLR) as the signal metric. An approximation to the LLR for the least reliable bit (LRB) in an 8-PSK modulation based on planar equations with fixed-point arithmetic is developed that is both accurate and easily realisable for practical BCM schemes. Through an error power analysis and an example simulation it is shown that the approximation results in less than 0.06 dB in degradation over the exact expression at an Es/N0 of 10 dB. It is also shown that the approximation can be realised in combinatorial logic using roughly 7300 transistors. This compares favourably to a look-up table approach in typical systems
