A trigger supervisor, implemented in VME-bus hardware, is described, which enables the host computer to dynamically control and monitor the trigger configuration for acquiring data from multiple detector partitions in a complex experiment

Lanza, R.

LeVine, M. J.

Scheetz, R. A.

Videbaek, F.

Wadsworth, B.

UNT Digital Library

BNL 39808THE TRIGGER SUPERVISOR: MANAGING TRIGGERING CONDITIONSIN A HIGH ENERGY PHYSICS EXPERIMENTBernard Wadsvvorth and Richard Lanza , %Laboratory for Nuclear Science, Massachusetts Institute of TechVpU/gyQ \ \; pip i;',Cambridge, MA 021S9 ir'bCl- 'M. J. LeVine and R. A. ScheetzPhysics Department, Brookhavm National Laboratory .J';!'•' 1 •••Upton, New York, 11978FlemmingVidebaek B N L ~ 3 9 8 0 8Physics Division, Argonne National LaboratoryArgonne, IL 60439iud?DE87 010444We describe a trigger supervisor, implemented in VME-bua hardware, which enables the host computer to dy-namically control and monitor the trigger configurationfor acquiring data from multiple detector partitions ina complex experiment.IntroductionExperiment E802 at BNL will study the complexspectra of particles produced in nucleus-nucleus interac-tions.. The-detector hardware required for this study iscomprised of several detector subsystems (for tracking,particle identification, calorimetry, etc.) referred to aspartitions.Each of the detector partitions may contributeto the first-level trigger which initiates gating and digi-tization of some 5000 measurement parameters for eachevent. The trigger logic for up to 16 partitions is col-lected into one system, the Trigger Supervisor, whichenables the host computer to dynamically control andmonitor the trigger configuration for the experiment.The Supervisor consists of a control module and16 partition modules in one triple-high VMEbus crate.An arbitration module and crate interconnect modulein the same crate make the Supervisor a resource avail-able to the master VME crate, providing communica-tion with the host and the crate readout controllers han-dling the front end electronics for the partitions. TheSupervisor's design keeps the insertion time down toapproximately 50 nsec.Functions provided by the Trigger Supervisor in-clude the following:• Provision for coupled (on beam spill) and uncou-pled (off-spill calibration, debug, test) modes ofoperation for each of the 16 partitions. Coupledpartitions share a common dead time, and un-coupled partitions have independent dead timesto allow for independent data streams. A first-level trigger from any coupled partition generatesgates for all coupled partitions.• Eight components in the first-level trigger fromeach partition; each may be individually enabledor disabled. Each trigger component may beprescaled by factors ranging from 1 to 2M.• Generation of gates/starts for front-end ADCs,TDCs, latches, etc.• Interrupt generation for crate readout controllers.• Record provided of pattern of trigger compo-nents present in the first-level trigger.• A transaction counter, updated by accepted trig-ger, may be used to assure integrity of eventsassembled from multiple fragments.• Second-level trigger (veto) logic is provided, in-cluding generation of fast clears for ADCs, TDCs,with no computer overhead. Veto survival is pro-vided for rare trigger components.• In a given partition, the relative delay betweenthe interaction trigger and the gates generatedfor the front end electronics is constant to within1 nsec independent of which partition initiatedthe first-level trigger.• Diagnostic features are included: computer read-out of all control registers including prescale fac-tors and a computer test mode to verify the cor-rect operation of all aspects of the Supervisor'soperation.The paper describes the implementation of thesefunctions, and highlights the more unusual design fea-tures.While the Trigger Supervisor has been designedto serve the needs of a specific experiment, the general-ity and flexibility it provides make it potentially usefulin other experiments involving complex detector sys-tems.Functional DetailsThe Trigger Supervisor's principal role is to useselected first-level trigger inputs, prescaled if desired, togenerate gates for a partition's ADCs and TDCs, sub-ject to appropriate busy logic. This operation takesplace in a manner which differs depending on whetherthe partition is coupled or uncoupled. A coupled par-tition's gates are generated whenever a trigger input isaccepted from any coupled partition; in other words, allcoupled partitions always generate gates for the sameevents. Gates are generated for an uncoupled partitionMASTER SIST9IBUTI0N OF THISonly when one of its trigger inputs is accepted. Busylogic is treated differently in the two cases as well: un-coupled partitions have independent busy latches, whichmay be reset by the microprocessor whenever its front-end electronics has been read out. The busy latch for acoupled partition is set synchronously with those of theother coupled partitions, and only cleared when data .for all coupled partitions has been read out.Each partition module provides for eight inde-pendent trigger inputs. Each input is independently en-abled/disabled under computer control. If the partitionis not busy, the enabled input is subjected to prescaling.Prescaling factors from 1 to 224 are possible.A. second role of the Trigger Supervisor is to pro-vide for second-level vetoes. This is accomplished byproviding a veto input on each partition module. Ineffect, a partition may withdraw its first-level triggerdecision at any time up to 1 /^sec following the trig-ger by issuing a veto. If an event is characterized, atthis second-level decision time, by having no outstand-ing triggers, fast clears are issued to the front-end elec-tronics, and the busy logic is reset at the appropriatetime.Any trigger component may be designated as a"Veto Survivor"; the occurrence of such a trigger over-rides any second-level veto decision. This provisionguarantees that rare events, e.g., beam events scaleddown by 106, are not discarded because, for example, adesired multiplicity threshold was not exceeded.A global veto is also provided. Intended to beused to discard events which have been corrupted bypost-pileup, it generates the fast clear sequence regard-less of the existence of Veto Survivors.ImplementationThe Trigger Supervisor, consisting of the controlmodule and up to 16 partition modules, is housed in atriple-high (9U) VME crate. An arbitration module andcrate interconnect complete the crate configuration. Oneach module, the PI backplane connector is devoted toVMEbus signals; the center row of the P2 connector isreserved for VME signals (not used here). The remain-ing rows of P2 are used for control signals between thecontrol module and the partition modules.The Trigger Supervisor logic is implemented part-ly in ECL-10KH in order to achieve an insertion time(interaction trigger in to gates out) of «s50 nsec, andpartly in LSTTL to achieve greater packing density andfunctionality and to keep the overall power dissipationwithin reason.In the following paragraphs, we limit the discus-sion to coupled partitions. An interaction trigger (as-sumed to be present for every event in coupled mode) issubjected to standardization (Figure 1) in order to guar-antee that the LSTTL devices in the partition modulebehave correctly. Standardized pulses have widths of 50nsec and are separated by a minimum of 125 nsec. Asystem busy synchronizer functions as the busy latch forthe coupled partitions and, further, insures that the re-lease of BUSY does not result in a truncated pulse. Theoutput of the synchronizer is the EVENT STROBE,which is used to time the gates generated by the parti-tion modules.Figure 2 traces the progress of a trigger com-ponent on the partition module "X" to the point of afirst-level trigger decision. Each trigger input consistsof a two-fold ECL AND, where one of the inputs is op-tional. If absent, this second input defaults to TRUE.The second level of gating requires an enable level (com-puter enable) and the EVENT STROBE described ear-lier. Prescaling, handled in the third level of gating, isimplemented out-of-line in order to avoid excessive in-sertion time. The prescaler increments on the trailingedge of each trigger; when it overflows, the logic acceptsthe following trigger, and presets the sealer in prepara-tion for another scale-down sequence. Eight such trig-ger components are wire-ORed to form the "X FIRSTLEVEL".This signal is wire-ORed on the P2 backplane(Figure 3) with similar signals from other coupled par-titions to form "SYSTEM FIRST-LEVEL". This signalis used by the Control module to set SYSTEM BUSY.A 10H102 receiver on the partition board produces UX/SYSTEM FIRST-LEVEL", which is logically identicalInteractionTrigger width andSeparationStandardizerClearFig. 1: Control module event strobe generationVHEDU3LOWIOHH5^ " " T / 1 10H105TRIGGER COHPONENTS I I cINPUTS >ENABLE XI10H105EVENT STROBEfro»CONTROL MODULELOGIC FOR SEVEN OTHERPAIRS OF X TRIGGER COHPONENTSX2A.X28 XBA.X88X FIRST LEVELFig. 2: Generation of X first-level decision in the partition X moduleto the backplane signal for the case of a coupled parti-tion. This signal is used to generate the output gatesfor the X partition, using DELAYED EVENT STROBEdistributed via the backplane to time the gates. DE-LAYED EVENT STROBE, used in this way, guaranteesthat the start of the gates at the output of any parti-tion board varies not more than 1 nsec, independent ofwhich trigger component initiated the event.The details of the second-level veto are shown inFigure 4. The X VOTE latch is set by the rising edgeof X FIRST-LEVEL. The partition veto logic can clearthis latch at any later time. X VOTE is wire-ORed onthe backplane with votes from other coupled partitionsto form SYSTEM VOTE. One ^ e c after X/SYSTEMFIRST-LEVEL, SYSTEM VOTE is clocked into a set oflatches which initiate the fast clear sequence or initiatethe interrupts to the microprocessors {distributed viafront panel outputs), depending on whether any votesare outstanding at this time.Partition veto is supplied by a front panel input,X VETO, which is disabled whenever a trigger compo-nent labelled as a veto survivor has contributed to XFIRST LEVEL.Great care has been taken in the implementationof the ECL wired-OR signals SYSTEM FIRST-LEVELand SYSTEM VOTE developed and distributed on thebackplane. Terminations at each end of the bus andSchottky diode clamps on the partition modules helpachieve generally clean signals. In addition, the logicwhich uses these signals is designed to be insensitive tothe trailing-edge glitches which result from the asyn-chronous release of the OR-bus by the participatingdrivers.Computer Access to Supervisor functionsSixteen-bit registers on the Control module in-clude the Coupled register, which determines which par-titions are coupled, the Busy register, which allows mi-croprocessors to determine which partitions are involvedin an event, the Event Counter, a transaction counterfor events involving coupled partitions, and Set-ClearSelect, which serves as a mask for operations on theBusy register. There is also a Function byte which isused to set and clear selected busy bits.XFIBST-LEVEL l»io! P2 BackplaneSYSTEM FIRST-LEVELWIBED-OH Of COUPLED FIRST-LEVEL)\ XCOUPLEOX/SYSTEHFIflST-LEVELFig. 3: System first-level decision generation by the partition X moduleX/SYSTEHFIHST LEVELX FAST CLEARP2 Backplane .SYSTEM VOTE(Wired-OR ofcoupled vote)Fig. 4: Second-level veto logic in partition XOn the Partition modules, several 8-bit registersallow Enable and Veto Override to be set, and a trans-action counter and trigger pattern register to be read.A Pulse register generates simulated triggers in all en-abled components. Finally, the 24-bit prescalers may beread and written.The Trigger Supervisor occupies 1024 bytes ofshort addressing space, and responds to both supervi-sor and user address modifiers. All functions may beaddressed as bytes; additionally, 16-bit registers maybe addressed as words.Address lines A0S..A08 are used to define thepartition board being selected. Hardware on the par-tition board compares these address lines with a 4 bitgeographical address encoded in the P2 backplane. Thiscomparison is only valid when accompanied by one oftwo partition enable signals generated by the addtassdecoding logic on the control module. One of theseis the SCALER SELECT signal which defines the ac-cess to the prescaler subspace of the partition addressspace. The PARTITION SELECT signal defines accessto the miscellaneous (non-sealer) functions on the par-tition boards.Summary and StatusA system has been described which allows themanagement of triggering conditions in an experimentwhere many detector subsystems areinvlolved. The sys-tem is presently under construction, and is expected tobe used in the experiment this Fall.AcknowledgmentThis work was supported by the U. S. Depart-ment of Energy under contracts DE-AC02-76CH00016and DE-AC02-76ER03069 (Division of Basic EnergySciences), and W-31-109-ENG-38 (Nuclear Physics Di-vision).DISCLAIMERThis report was prepared as an account of work sponsored by an agency of theUnited States Government. Neither the United States Government nor any agencythereof, nor any of their employees, makes any warranty, express or implied, orassumes any legal liability or responsibility for the accuracy, completeness, or use-fulness of any information, apparatus, product, or process disclosed, or representsthat its use would not infringe privately owned rights. Reference herein to any spe-cific commercial product, process, or service by trade name, trademark, manufac-turer, or otherwise does not necessarily constitute or imply its endorsement, recom-mendation, or favoring by the United States Government or any agency thereof.The views and opinions of authors expressed herein do not necessarily state orreflect those of the United States Government or any agency thereof.

The trigger supervisor: Managing triggering conditions in a high energy physics experiment

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The trigger supervisor: Managing triggering conditions in a high energy physics experiment

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