Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis

Abstract

This paper presents a new layout parasitics extraction paradigm, symbolic extraction, for use in layout-aware analog synthesis methodologies. Unlike traditional post-layout extraction, symbolic extraction extracts layout parasitics in symbolic form from parameterized layouts. As a result, parasitic values can be calculated directly from given circuit and layout parameters. In layout-aware circuit synthesis process, tasks of time-consuming layout re-gerenarion and re-extraction can be replaced by this fast parasitics calculation step. In the paper, we discuss how to integrate symbolic extraction into the existing analog design flow and how symbolic extraction can be implemented