This Project is sponsored by The MITRE Corporation to develop an FPGA implementation of a Log Likelihood Ratio (LLR) soft decision demapper for a High Data Rate (HDR) modem. The main goal of this project is to add support for higher order modulation up to 32APSK for HDR and high bandwidth efficiency. Through preliminary research, several DVB-S2 soft decision LLR algorithms are investigated for different modulation schemes in order to decide which algorithm will be implemented in synthesizable Hardware Description Language (HDL). Algorithms are analyzed based on performance simulation in MATLAB and complexity analysis. The goal is to improve the performance of current system and provide recommendations for future designs of the soft decision demapper for DVB-S2
