Control function verification is an important task in current engineering design. Traditional researches usually focus on the final function validation when the control system has already been implemented on a hardware controller. However, it would be more useful if design errors are found in earlier stages of design. Logic diagram, as a popular middle medium, plays a critical role in the current design practices, especially for medium-sized and large-sized control systems. Therefore, verification of the design specifications of the logic diagrams is an interesting topic in order to find and eliminate the design errors in an early stage. In this thesis, we provide a viable approach to verify the design functions of the logic diagrams which is based on the modular supervisory control of Discrete-Event Systems. We create models for basic logic gates and introduce buffers to obtain automaton representation of logic diagrams After converting the informal verbal specifications to automata, we can verify whether the logic diagram satisfies these specifications with the help of TTCT (a computer program based on automata for analysis and design of supervisory control systems). A formal proof of controllability and a semi-formal proof of nonblocking property are given. An industrial-sized example is studied to demonstrate the feasibility of our methodology
