Physical routability constraints such as legal location checking and excessive number of vias are usually ignored in most of the clock tree algorithms. These Constraints could make an abstract clock tree difficult to route in practice and cause important manufacturability and reliability challenges. Therefore the final clock tree layout specifications can be seriously deviated from the expected ones. Vias have major impact on circuit reliability and manufacturing yield. The variability in via resistance is becoming an increasing concern in nanotechnologies. In this thesis a practical frame work is proposed to construct the clock tree network under via constraint. We propose an algorithm that minimizes the number of bends that is closely related to the number of vias. The proposed algorithm is able to construct a zero skew clock tree with at most one bend branch merging. By performing simultaneous wire sizing and clock tree construction, the algorithm effectively reduces the number of bends at the expense of a small increase in capacitance. Furthermore, the number of vias is also controlled by considering a pre-specified pattern to route the internal clock tree edges. The impact of the pattern routing is taken into account in the early clock distribution design phase. We introduce a probabilistic routing demand estimation method to integrate the expected routing demand of the clock net with other clock tree optimization metrics. A new demand driven cost function is exploited in network topology generation as well as branch point embedding stages of a zero skew clock tree algorithm to reduce the number of vias. Our experiments show considerable improvements in the total number of vias. 28% reduction in the number of vias is obtained while the total clock tree wire length is reduced by an average of 8%. The post-routing induced clock skew is also controlled efficiently
