Here we reported a novel technology using parylene-cross-linking structure to achieve on-chip air-gap thermal isolation for microfluidic system-on-chip (SOC) applications. Two applications based on this technology, on-chip continuous-flow polymerase chain reaction (PCR) and on-chip temperature gradient liquid chromatography (LC) were successfully demonstrated. Device thermal performance in each example was characterized. Results showed that our technology not only provides excellent on-chip thermal isolation but also its simplicity of integration with other on-chip components makes versatile microfluidic SOC applications feasible

Chen, Yang

Shih, Chi-Yuan

Tai, Yu-Chong

Caltech Authors - Main

362.1 
PARYLENE-STRENGTHENED THERMAL ISOLATION TECHNOLOGY FOR 
MICROFLUIDIC SY STEM-ON-CHIP APPLICATIONS 
Chi-Yuan Shih, Yang Chen and Yu-Chong Tai 
Electrical Engineering Department, California Institute of Technology 
MC 136-93, Pasadena, CA 91 125, USA, E-mail: cyshih@caltech.edu 
ABSTRACT 
Here we reported a noveI technology using 
parylcne-cross-linking structure to achieve on-chip air- 
gap thermal isolation f i x  microfluidic system-on-chip 
(SOC) applications. Two applications based on this 
technology, on-chip continuous-flow polymerase chain 
reaction (PCR) and on-chip temperature gradient liquid 
chromatography (LC) were successfully demonstrated. 
Device thermal performance in each example was 
characterized. Results showed that our technology not 
only provides excellent on-chip thermal isolation but 
also its simplicity of integration with other on-chip 
components makes versatile microfluidic SOC 
applications feasible. 
Keywords: Parylene, Thermal isolation, Microfluidic, 
On-chip, Chromatography 
INTRODUCTION 
Silicon is a fundamental structure material in 
MEMS with a very high thermal conductivity of 148 
W/m-K (compared with 73 W/m-K of iron). This 
specific thermal property guarantees great on-chip 
temperature uniformity, however it also generates 
design complexity for applications where multiple 
temperature zones are required on a single silicon chip. 
Some representative SOC applications that require 
multiple on-chip temperature zones are polymerase 
chain reaction [ 1 J and temperature gradient liquid 
chromatography [2]. Ideally, for best temperature 
uniformity on each temperature zone, no silicon 
connection should remain between temperature zones 
and therefore a wafer-thickness-deep, temperature- 
zone-surrounding thermal isolation structure needs to 
be used on the chip. While several thermal isolation 
technologies have been developed, the aerogel or 
porous-silicon structure in general provides only 
vertical direction thermal isolation [3]; floating 
membrane structure which uses thin dielectric layer to 
hold frcestanding temperature zone is mechanically 
fragile and cannot stand much stress and strain 
encountered during device fabrication or testing 
procedures [4]; oxide-filled trench structure has only 
limitcd thermal isolation efficiency due to the still high 
thermal conductivity of oxide (1.4 Wlm-K for silicon 
dioxide) and the limited oxide thickness [ 5 ] .  To attack 
these shortcomings, we propose here to use a novel 
parylene-cross-linking thermal isolation technology. 
In the past decade, parylene was used extensively as 
a MEMS structure material to build microfluidic 
system components including sensors and actuators [6- 
91. Because parylene is a flexible polymer material (an 
elongation break of 200 %) and has a very low thermal 
conductivity of 0.08 W/m-K (compared with 0.03 
W/m-K of static air), using parylene to build thermal 
isolation structure can provide crucial benefits such as 
robust mechanical support to the temperature zones 
and high thermal isolation efficiency, which in general 
cannot both be provided at the same time by other 
thermal isolation technologies. As wili be shown 
below, we have successfully developed the parylene- 
strengthened thermal isolation technology and 
demonstrated its applications, in the field of 
microfluidic system-on-chip. 
DESlGN AND FABRICATION 
Fig. 1 shows the process flow of the proposed 
parylene-strengthened thermal isolation technology. 
Grow oxide, deposit and pattem metal, pattem 
front side and back side oxide, backside DRIE 
*I Je553& L . *-2 al.. I 
Deposit and pattern parylene, deposit and 
pattern photoresist 
Front side DRIE, deposit and pattern parylene 
Backside DRIE, dicing, release photoresist, 
0 Parylene Silicon Oxide Photoresist 
Fig. I :  Process flow of palylene-slrengrhened fherrnal 
isolation technology. 
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This technology not only provides lateral on-chip 
thermal isolation but also it allows microfluidic 
channel and electrical path connection between 
temperature zones. Process starts with growing 1 F]-m 
SiOz layer on both sides of 4-inch silicon wafers 
(thickness: 525 +/- 25 pm) by thermal oxidation. 
Metal is then deposited and patterned on the wafer 
front side. Front side oxide is patterned with buffer HF 
(Transene, Danvers, MA). Backside oxide is then 
patterned to define the 1OOpm-diameter liquid access 
holes and 150pm-wide air gap for thermal isolation. 
Without removing photoresist on the backside oxide, 
DRIE (deep reactive ion etching) is used to etch 
backside silicon for 450 pm. 4pm-thick parylene-C 
(Specialty Coating Systems, Indianapolis,, IN) is then 
deposited and patterned with oxygen plasma on wafer 
front side. 25 pm photoresist A24620 (Clariant, 
Somerville, NJ) is deposited and patterned on wafer 
front side to form microfluidic channel sacrificial layer. 
A 1 00°C-3hr baking is carried out to avoid photoresist 
bubbling from latter thermal treatment. Front side 
oxide and photoresist are then used together as DRIE 
mask to etch down silicon for a 30pm-deep, 15pm- 
wide trenches with a mushroom profile in the trench 
bottom (by a modified DRIE Bosch process [lo]). The 
trench-mushroom structure here is used as the 
anchoring space for I;aryiene thin film deposition. 10 
pm parylene is then conformally deposited on wafer 
front side, filling up the trenches and covering 
photoresist structures. Parylene is then patterned with 
oxygen plasma. DRIE is carried out on wafer backside 
again to etch through the silicon wafer for the liquid 
access hoIes and thermal-isolation air gaps. Finally, 
the wafer is diced into 1.lcmxl.lcm chips and 
photoresist inside the column is dissolved by SOOC- 
24hr acetone bath through backside liquid access holes. 
Fig. 2a shows the schematic plot of parylene-cross- 
linking structure. Parylene layer is deposited into 
silicon trenches created by DRIE to provide robust 
parylene anchoring. Since parylene has a high 
elongation break and a very low thermal conductivity, 
parytene-cross-linking structure provides a durable 
Fig. 2: a. Illusfration of parylene-cross-linking 
stmcfure, b. a photograph showing 150,um-wide 
through-wafer air gap and the silicon temperature 
zone (center piece). 
mechanical support to temperature zones while not 
much heat will be conducted through the structure 
itself. Fig. 2b shows a silicon temperature zone 
defined by 150pm-wide air gap. Fig. 3a shows the 
cross-sectional view of the anchored parylene column 
which is 100pm-wide and 25pm-high. Fig. 3b shows 
the fabricated microfluidic channel on top of a parylene 
membrane running across the thermal isolation air gap 
from one temperature zone to the other. 
I 
Fig. 3: a. Cross-sectional view of the anchored 
palylene column. b. fabricated microfluidic channel 
running across thermal isolation air gap. 
APPLICATION AND DISCUSSION 
Two examples of microfluidic SOC application 
using proposed parylene-strengthened thermal isolation 
technology were successfully carried out as follows. 
On-chip continuous-flow PCR 
Polymerase chain reaction requires the DNA sample 
solution to periodically pass through three temperature 
zones including the high temperature zone (94 OC) for 
double-strand DNA (dsDNA) melting, the low 
temperature zone (60 "C) for primer annealing and the 
medium temperature zone (72 'C) for primer extension 
[ 11. With the developed thermal isolation technology, 
three temperature zones defined by air gaps were 
created on the silicon substrate. Each temperature zone 
had its individual resistive heater for precise 
temperature control. As shown in Fig. 4a, 10 PCR 
cycles were prepared on a 0.8cmx0.8cm chip area. 
PCR time ratio among the three temperature zones was 
defined by the fluidic channel length in each 
temperature zone. Fig. 4b then shows the thermal 
image of the powered up PCR temperature zones taken 
by InfraScopeTM system. 
Fig. 4: a. Continuous-flow PCR device uith 10 PCR 
cycles, b. thermal image of a powered up PCR device., 
remperalure was read out from heater resistance via 
TCR (temperature coefficient of resistance) data. 
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1184 
382.1 
On-chip temperature gradient liquid chromatography 
MEMS technology is a fundamental tool tu carry out 
the miniaturization goal of modern HPLC system [l I]. 
PVE Parylene Silicon= Oxide Bead 
While most researchers have pursued solvent- 
controlled MEMS LC [ 121, temperature gradient LC 
(i.e., changing the LC column's temperature as a 
function of time to achieve analytes elution) has never 
been demonstrated in MEMS before [13]. In fact, we 
believe MEMS temperature gradient LC is extremely 
attractive because of the ease of achieving on-chip 
temperature control by MEMS [14]. Based on this 
motivation, we used the proposed process flow to 
fabricate the first chip-based temperature gradient LC 
system which integrated LC column, electrochemical 
* =  
m .  
, 
"20 30 40 50 60 70 80 90 100 
Column temperature ('cc) 
Fig. 6: Thermal isolation efliciency: (w) column 
without ihermal isolation structure. (U] column 
surrounded b31 parylene-str-engthened air-gap thermal 
isolation structure. Thermal isolation structure 
effecfively reduced column-zone heating power 
consumption by 58%. 
sensor, resistive heater and parylene-strengthened 
thermal isolation structure on a single silicon chip as 
shown in Fig. 5. 
Thermal isolation efficiency of the parylene- 
strengthened air-gap structure was then studied. 
Results showed that the thermal isolation structure 
effectively reduced column-zone heating power 
consumption by 58% (Fig. 6 )  and the off-column 
temperature rise (compared with on-column 
temperature rise) by 67% (Fig. 7). With the off- 
column cooling function available, it is feasible to 
layout the electrochemical sensor in the cooling area 
when analyte sensing needs to be done at low 
background temperature. Chip thermal performance 
can be further improved by reducing the temperature- 
zone area or increasing the air-gap width. Fig. 8 then 
shows the successful separation and detection of 
derivatized amino acids using our chip-based 
temperature gradient LC system [ 151. 
"SO 100 IS0 200 250 300 350 400 
Input power (mW) 
Fig. 7: On-chip demperuture rise ( A r )  spa rial 
distribution during temperature gradient operation: 
(U) air-gap-surrounded column area, (0) off-column 
area. Compared with on-column area, temperature 
rise in the off-column urea was reduced by 67 %. 
CONCLUSION 
A novel thermal isolation technology using 
parylene-cross-linking structure to achieve on-chip air 
gap thermal isolation was demonstrated. Two 
applications based on this technology, on-chip 
continuous-flow polymerase chain reaction and on- 
chip temperature gradient liquid chromatography were 
successfully carried out. Devices thermal performance 
was characterized. Results showed that our technology 
not only provides excellent on-chip thermal isotation 
efficiency but also its simplicity of integration with 
other on-chip components makes versatile microfluidic 
SOC applications feasible. Future work is focused on 
improving fluidic column structure robustness 
especially around the air gap region so to make more 
high pressure applications feasible. 
TRANSDUCE RS'05 
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1 I85 
3B2.1 
120 I 
SER GLY ALA 
I U  
I ‘20 
0 2 4 6 8 10 
Elution time (min) 
Fig. 8: Chromatogram showing derivatized umino acids sepuruted using temperature gradient elution: (black line) 
temperature gradient elution with column temperature scanning from 25 ‘C at 0 min to 65 “C at 11 min with a slope of 
3.6 ‘C/min, @ay linej isothermal elution with column temperaturefixed at 25 ‘C throughout the separation, (dash h e )  
femporul temperature gradient which was applied to the column during separation. 
ACKNOWLEDGEMENTS 
This work was supported by the NSF Center for 
Neuromorphic Systems Engineering (CNSE) at 
Caltech. The authors would also like to thank Mr. 
Trevor Roper for his assistance in processing. 
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TRANSDUCERS’OS 
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Parylene-strengthened thermal isolation technology for microfluidic system-on-chip applications

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Parylene-strengthened thermal isolation technology for microfluidic system-on-chip applications

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