Accelerated lifetime tests have been performed on integrated planar GaAs Schottky diodes that were bonded to quartz substrates upside-down with a heat-cured epoxy. Results at 175°C, 200°C, and 240°C were analyzed using the Arrhenius-lognormal model. These tests predict a room temperature MTTF of 3x10^8 hours, a value that is comparable to conventional high-frequency planar Schottky diodes. This result demonstrates that the use of an appropriate epoxy to obtain GaAs devices on quartz substrates does not significantly reduce the lifetime of the devices

Dengler, R.

Humphrey, D.

Kayali, S.

Lee, T.

Lin, R.

Mehdi, I.

Pease, A.

Scherer, A.

Caltech Authors - Main

~ 
Submitted to the 1997 GaAs REL Workshop, October 12", 1997 
.bccelerated lifetime testing and failure analysis of 
quartz based GaAs planar Schottky diodes 
-9 R Lin I. hlehdi, A. Pease, R. Dengler, D. Humphrey, T. Lee, A. Scherer", and S. Kayali 
Jet Propulsion Laboratory 
*California Institute of Technology 
Address inquiries to: 
Voice (818) 354-2001, Fax (818) 393-4683 
~ I. Mehdi, M / S  168-314, JPL, 4800 Oak Grove Drive, Pasadena, CA 91109 
I 
~ ABSTRACT 
analyzed using the 
tests predict a 
I L Introduction 
For very high frequency applications, quartz is a 
desirable substrate material, because it has lower loss 
circuit is bonded upside-down onto a 50 micron thick 
quartz substrate with a heat-cured epoxy [3]. This 
bonding agent also fills the air gap under the fingers, 
and this may be a factor in the device's reliability. 
Finally, all of the GaAs substrate is etched except for 
two small mesas around the active region with the 
two planar diodes [41. 
I 50 micron QBptz- - - A H e a t  - - epoxy 
n+ GaAs 
Channel SI GaAs 
50 micron Quartz 
and lower dielectric constant than GaAs. One 
possible method ( f obtaining semiconductor devices 
on quartz substratc i s is to use a bonding agent such as Figure I :  Cross-sectional schematic of the starting and ending point of the QUID process. 
t epoxy. A techi'que, named QUID (for Quartz substrate Up-sideI own Integrated Device), has been II. Accelerated Lifetime Procedure 
developed t o  prtlduce GaAs Schottlq diodes on 
quartz substrates 1 for millimeter and submillimeter 
wave applications [1,2]. In this technique, planar 
GaAs Schottky c iodes are mounted up-side-down 
onto quartz subs1 ates for space-borne radiometers 
that operate at fiequencies up to 640 GHz. After 
successful perfor in ance demonstration, it is now 
desirable to study1 the failure mechanisms associated 
with such strucmbs. 
The model used for the .accelerated lifetime tests 
is the Arrhenius-lognormal model. This model is 
widely used for GaAs devices [5], and states that the 
failure times for a batch of devices have a l o g n o d  
distribution about the median time to failure (the time 
for 50% of the devices to fail). This median time to 
failure, in turn, is related to absolute temperature by 
the relation 
I 
Figure 1 shovls a cross-sectional schematic of the t=toexp(EJkT), (1) 
e anode of the Schottky contact is 
at the end of a long strip 
a central air gap. Two 
where t is the mean time to failure, E, is the activation 
energy measured in eV, k is Boltzmann's constant, 
and T is the absolute temperature. such diodes ate arranged in an antiparallel 
configuration. Fol/lowing the integration of the diode 
with the RF miiwostrip filter circuitry, the entire 
Submitted to the 1997 GaAs REL Workshop, October 12&, 1997 
An automated system was used to conduct the 
accelerated lifetime tests [6]. The QUID structures 
were placed unbiased in a nitrogen-purged high- 
temperature oven for an extended period of time. 
The temperature was slowly ramped up from room 
temperature with the devices already mounted inside 
the oven. Device IV characteristics were monitored 
in-situ, once every hour, with a computer-controlled 
data-acquisition system. Nominally fifteen devices, 
or thirty anodes, were tested at each of three 
temperatures: 175"C, 200"C, and 240°C. These 
devices were mounted onto ceramic chip carriers 
using two-part epoxy and gold wire bonds, and 
subsequently placed in a high-temperature wiring 
fixture designed to withstand 250°C. 
In defining what constitutes a failure for the 
QUID structures, we use a failure criteria based on 
the DC IV characteristics that may help us predict the 
device's performance degradation at RF frequency 
applications. A device is considered to have failed if 
any of three conditions is met: (1) diode ideality 
factor, q, changes by lo%, (2) diode series resistance, 
R, changes by 20%, (3) diode turn-on voltage, V, 
(voltage where current is 1 pA), changes by. more 
than 20%. 
The zero percentage change baseline for each of 
these three parameters is calculated by averaging a 
diode's parameter during the first few measurements 
at the test temperature. This is to smooth out some of 
the noise due to measuring errors. For each device, 
when any of its three parameters meets the failure 
criteria, the time since the beginning of the test 
temperature period is recorded. The failure times are 
plotted on a lognormal graph paper, and an apparent 
linear regression line is constructed to determine the 
median time to failure and the standard deviation at 
each temperature. 
BI. Results and Discussion 
Figure 2 shows the lognormal distribution plots 
for the three lifetime tests. The standard deviation is 
0.2 for the 175°C test, and 0.6 for both the 200°C and 
240T test. The three median times to failure are 
then plotted against temperature ro give the Arrhenius 
plot, shown in Figure 3. The best-fit line, when 
extended to 23"C, gives an estimated mean time to 
failure at room temperature of 3x10' hours. This is 
comparable to the values obtained in previous studies 
of planar Schottky diodes at the University of 
Virginia [7,8]. Assuming a single failure mode is 
responsible at all three temperatures, the slope of the 
line gives an activation energy of 0.94 eV. 
I i r  I 
1 5  2 0 4 0 6 0 8 0  9 5 9 3  
Cumulative Failures (%) 
Figure 2: Device failures at I75"C, ZOO'C, and 
240'C. Failure criteria is either ,Aq,>lO%, 
lARsl>20%, or ,AVO1>2O%. 
1 O'O 
io9 
lo8 
1 10' 
E io5 
= lo4 
lo3 
ld 
10' 
2 lo6 
v 
t 50 100 150 m 2% 
23°C Temperature eC) 
Figure 3: Arrhenius Plot for JPL 640 GHz QUIDs 
It must be noted that the test performed at 175°C 
was not conducted with the same high-temperature 
fixture that was used in the other two tests, but with 
standard circuit boards. Data from this test showed 
that all devices experienced a common degradation 
cycle around 600 hours. Since such a behavior was 
not observed for the test performed with the high- 
temperature fixture, it is assumed @at the unexpected 
behavior in the 175°C test data was caused by 
degradation of the circuit board rather than the QUID 
structures. This may also explain the lower standard 
deviation value for this test in figure 4. It is likely 
that the failure times at 175°C are under-estimated, 
and that we have calculated a conservative value for 
the MTTF- at room temperature. 
20 
~ 
Submitted to the 1997 GaAs REL Workshop, October 12*, 1997 
Figure 4: SEMkhoto of a QUID structure after 
240°C life(1ime test. This device failed 
catastrophically,l and there is a crack in the epoxy 
Grmi G ~ A S  mesas. 
Figure 5: SEM photo of a QUID structure after 
240°C lifetime teJ t. This device degraded gradually, 
and shows no SI ,ns of cracks in the GaAs mesas. 
An attempt was made to determine the 
mechanisms that ii)rere responsible for device failures. 
Following the acclelerated lifetime test, devices were 
inspected with  an^ optical microscope and a scanning 
electron microsco e. The SEM analysis showed that 
there are at least t’ o types of failure mechanisms, and 
that they are relatipd to different failure paths. Figure 
4 shows a device that failed catastrophically (that is, 
its IV characteristic changed abruptly), and figure 5 
shows a device tliat failed gracefully (that is, its IV 
parameters slowly degraded before it met the failure 
criteria). 
F 
The observed1 crack in figure 4 seem to be along 
the length of the/ two fingers in the central epoxy 
region, and along ia crystal plane in the semiconductor 
region, but no suqh crack is found in figure 5. If this 
mechanical defonpation reached the Schottky contact 
region, it may have caused the abrupt electrical 
change. The high-temperature stress possibly caused 
a structural stress buildup before it was released in 
the form of a catastrophic crack. Currently we are 
investigating other non-structural failure mechanisms 
that might be responsible for the devices that failed 
with gradual degradation. 
IV. Conclusions 
Based on results from accelerated lifetime tests at 
three different temperatures, the 640 GHZ QUID 
circuits were determined to have a room temperature 
MTTF of 3x10’ hours, with an activation energy of 
0.94 eV. Based on the SEM inspections, it was 
shown that there is a correlation between cracks in the 
device structure and catastrophic failures in the 
electrical behavior. Other failure mechanisms are 
responsible for non-catastrophic failures, since 
structural deformation was not observed for all 
devices that failed with gradual degradation. Results 
from further reliability tests and failure analyses will 
enable us to better understand these mechanisms. 
The MTTF values obtained from this work show that 
the QUID process can be a useful technique to obtain 
GaAs devices on non-semiconductor substrates. This 
technique could also be usehl for other applications 
where a dissimilar substrate is required. 
V. Acknowledgments 
The authors would like to acknowledge S. Martin 
for help in the device fabrication, B. Fujiwara for 
wire bonding, and K. Evans for the SEM images. We 
are also grateful to Dr. Peter Siegel and Karen Lee for 
technical discussion and for the support of this 
investigation. The research described in this paper 
was carried out by the Jet Propulsion Laboratory, 
California Institute of Technology, under a contract 
with the National Aeronautics and Space 
Administration. 
VI. REFERENCES 
[l] I. Mehdi, S. C. Martin, R. 3. Dengler, R. P. 
Smith, and P. H. Siegel, “Fabrication and 
performance of Planar Schottky Diodes with T- 
Gate-Like Anodes in 200-GHz Subharmonically 
Pumped Waveguide Mixers,” in IEEE 
Microwave and Guided Wave Letters, Vol. 6, 
[2] I. Mehdi, T. H. Lee, D. A. Humphrey, S. C. 
Martin, R. J. Dengler, J. E. Oswald, A. Pease, R. 
P. Smith, and P. H. Siegel, “600 GHz Planar- 
NO. 1, pp. 49-5 1. January 1996. 
21 
Submitted to the 1997 GaAs REL Workshop, October 12”, 1997 
Schottky-diode subharmonic waveguide mixers,” 
in IEEE MTT-S 1996 Digest, pp. 311-319. 
[3] The epoxy used is EPOTEK 301-2. 
[4] I. Mehdi, M. Mazed, R. Dengler, A. Pease, M. 
Natzic, and P. H. Siegel, “Planar GaAs Schottky 
diodes integrated with quartz substrate circuitry 
for waveguide subharmonic mixers at 215 GHz,” 
in IEEE Intl. Microwave Symp. Digest, pp. 719- 
782,1994. 
[5] S. Kayali, G. Ponchak, R. Shaw, ed., GaAs 
MMIC Reliability Assurance Guidelines for 
Space Applications, JPL Publication 96-25, pp. 
6-14, Dec. 15, 1996. 
[6] R. Lin, “Reliability and Failure Analysis of Sub- 
micron T-anode GaAs Schottky Diodes with 
Quartz Substrates,” B.S. Thesis, California 
Institute of Technology, pp. 16-19, June 1997. 
[7] S. M. Marazita, “A Reliability and Failure 
Mechanism Analysis of Planar and Whisker- 
contacted GaAs Schottky Diodes,” B.S. thesis, 
University of Virginia, 1994. 
[SI J. L. Bowers, “Reliability of Planar GaAs 
Schottky Diodes,” M.S. Thesis, University of 
Virginia, 1993. 
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