'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10^(-12). It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110μm^2
