Models for describing the gate-source and gate-drain capacitances' variation along a resistive load line have been proposed. They are charge conservative and consistent with the small-signal model at bias points along the load line. The extraction procedure for the models' parameters is fast and intuitive. The models can be implemented easily in most circuit simulator programs

Leong, Y. C.

Weinreb, S.

Caltech Authors - Main

THlE-3 
EMPIRICAL LOAD-LINE CAPACITANCE MODELS FOR HEMT 
Y.C. Leong’ and S. Weinreb2 
U. of Massachusetts, 619 Lederle GRC, Amherst, MA 01003 
2Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109-8099 
1 
ABSTRACT 
Models for describing the gate-source and 
gate-drain capacitances’ variation along 
resistive load line have been proposed. They 
are charge conservative and consistent with 
small-signal model at bias points along the 
load line. Extraction procedure for the 
models’ parameters is fast and intuitive. The 
models can be implemented easily in most 
circuit simulator programs. 
INTRODUCTION 
The gate-source and gate-drain capacitances of 
HEMT have long been determined to have dual 
voltage dependency. Expressions for these 
capacitances as hnctions of two voltages have 
been published. However, small-signal 
linearization of the charge hnctions that are 
derived from these capacitance fbnctions will 
introduce transcapacitances [ 11. These extra 
elements cause discrepancy between the large- 
signal and small-signal models. A recent 
transistor model proposed in [2] is consistent and 
charge conservative. However, it requires a new 
topology for the intrinsic small-signal equivalent 
circuit model. Very often, the constant 
capacitance or junction capacitance models are 
still used. But in these two cases, variation of 
the capacitances with output voltage swing is not 
modeled. 
MODEL DESCRIPTION 
In this paper, empirical models for the gate- 
source and gate-drain capacitances will be 
proposed. These models have only single 
voltage dependency and they track the 
capacitances’ variation along a resistive load line 
in the IV plane of the HEMT. In this way, the 
influence of the output voltage on the 
capacitances can be modeled by using only the 
local voltages of the capacitors. They are charge 
conservative and the nonlinear model will be 
consistent with the common small-signal model 
at bias points that are along a resistive load line 
in the IV plane. 
The extraction procedure for the models’ 
parameters is straightforward and can be done 
using commonly available spreadsheet programs. 
As the capacitance hnctions are only one 
dimensional, the time needed to extract the 
capacitance models is very fast and the fitting is 
of good accuracy. The models also give an 
intuitive picture of the behavior of the FET 
during large-signal excitation since fitting is done 
directly with the measured capacitances’ 
variations instead of the S-parameters. 
These models can be implemented easily in most 
circuit simulators as simple charge sources across 
the capacitors’ terminals or as single-voltage 
dependent capacitors. The load-line models had 
been used to analyze a 47 GHz HEMT frequency 
tripler and good agreement has been obtained 
between the measured and modeled results. 
0-7803-5687-X/00/$10.00 0 2000 IEEE 
1385 
2000 IEEE M7T-S Digest 
These models are not global but they are 
application specific. They are best used in 
applications where the loading of the circuit can 
be approximated by a resistive load line over the 
frequency range of operation of the circuit. They 
are not intended to be used as a global model for 
foundry distribution. 
CAPACITANCE MODELS 
The expressions that are used to fit the gate- 
source and gate-drain capacitances along a 
resistive load line in the intrinsic IV plane are 
listed as follows: 
These expressions are well bounded in either 
direction of the local voltages, minimizing the 
possibility of causing convergence problem 
during nonlinear simulation. 
To extract the parameters of the capacitances, 
cold FET method [3] is first used to obtain the 
parasitic resistances. Intrinsic IV characteristics 
of the HEMT can then be obtained from 
transforming extrinsic values or through 
automated measurements of the HEMT. From 
the IV characteristics, target biasing point and 
specific resistive load line can be identified based 
on the intended application. Multi-bias S- 
parameter measurements are performed and 
conventional small-signal equivalent circuit!; are 
extracted using hothold FET method [3] for 
each intrinsic bias point. The target resistive load 
line is mapped onto the gate-source and gate- 
drain capacitance planes in the intrinsic voltage 
space. Equations (1)-(7) can then be fil.tted 
against the mapped load line using commonly 
available spreadsheet programs. 
Asymptotic behavior of the capacitances can be 
used as constraints to help in the fitting of the 
parameters. Voltages and gradients at the points 
of inflexion along the mapped load line in the 
capacitance planes can also be used to estimate 
the initial values for the r-parameters. Higher 
order terms could be used in the p-expressions 
for better fitting of the gradients across volta,ges 
but it is usually not required. GaAs and I’nP 
HEMTs with gate-length of 0.1-0.15 pm and 
gate-width of 50-200 pm have been fitted easily 
for class A power amplifier and active fiequericy 
multiplier applications using these expressions. 
EXPERIMENTALRESULTS 
A 47 GHz MMIC frequency tripler was analyzed 
in HP MDS using the above expressions to 
model the device’s capacitances. The chip uses a 
200 pm wide GaAs 0.15 pm HEMT device that 
is biased near pinched-off condition. Low 
impedance is presented at the output of the 
device at the fbndamental and second harmonjc 
frequencies. After accounting for the parasitic 
resistances, a 5-Ohm load line was first selected 
to approximate the output loading conditiori. 
Foundry-supplied DC model was used for 
modeling the IV characteristics of the device anti 
the load-line capacitance models were entered as 
charge fbnctions in the HP MDS circuit 
simulator. 
1386 
280 
260 
240 
220 
200 
a 160 
120 
100 
80 
60 
p 3 o  
8 1 4 0  
Y 
230 
21 0 
19!, 
g-170 
cn 150 
8130 
Y 
110 
90 
70 
50 
40-1 T !  ! ! !  I I f !  I -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 
-1.4 -1.2 -1 -0.8 -0.6 0 . 4  -0.2 0 0 2  0.4 0.6 Local wltage across capacitor (Vgs) 
vgs (V) 
v Measured - Modeled 
Figure 1. 
plane. load-line model. 
5-Ohm load line mapped onto Cgs Figure 3. Fitting of Cgs capacitance using the 
100 
go 
80 
70 
G 6o 
840 
50 
30 
20 
10 
0 
-7 -6.5 -6 -5.5 -5 4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 
Vgd (VI 
30 
28 
26 
24 
g 2 2  
g 2 0  
0 18 
16 
14 
12 
10 
-4.6-4.44.2 -4 -3.8-3.6-3.4-3.2 -3 -2.8-2.6-2.4-2.2 -2 
Local voltage across capacitor (VN) 
V Measured - Modeled 
Figure 2. 5-Ohm load line mapped onto Cgd 
plane. load-line model. 
Figure 4. Fitting of Cgd capacitance using the 
Figure 1 shows the 5-Ohm load line being 
mapped onto the gate-source capacitance plane 
while figure 2 shows the mapped load line in the 
gate-drain capacitance plane. Figure 3 shows the 
result of the fitted Cgs model against the mapped 
load line for the gate-source capacitance and 
figure 4 shows the result of the fitted Cgd model 
against the mapped load line for the gate-drain 
capacitance. To illustrate the typical values of 
the parameters, a set is listed in Table 1. Figure 
5 shows the measured output power of the 
frequency tripler against the modeled 
performance by incorporating the load-line 
capacitance models and the constant capacitance 
model. 
From the illustrations, good fit has been achieved 
by using the proposed models on the measured 
capacitances’ variation along the load line (<5% 
error in both cases). Good agreement between 
the measured and modeled performance of the 
frequency tripler has also been obtained by 
incorporating the proposed load-line capacitance 
models in the nonlinear simulation. 
The device’s dynamic load line of the entire 
circuit was also evaluated after implementing the 
device model. It was found that the average 
1387 
resistive path has a slope of about 10 Ohms. The 
models were refitted with the 10-Ohms load line 
and the circuit was re-simulated. It was 
Cgs Cgso Cgsp Cgsn Cgsa rl0 r11 rzo r21 r30 
5-Ohm -35.1 122.2 42.9 11.8 3.0 3.8 1.2 2.5 -2.4 
observed that there is little change in both 
simulation result and the final profile of 
dynamic load line. 
5 
4 
3 
2 
A 
I% s 
L O  
n $1 
-2 
-3 
-4 
-5 
42 43 44 45 46 47 48 49 50 51 52 
Frequency (Gk)  
r31 
8.4 
the 
the 
I Measured X Constant C a p  Load-line Model 
Figure 5 .  Modeled output power for frequency 
tripler using the load-line models and constant 
capacitance model. 
CONCLUSION 
parameter extraction procedure is fast and 
intuitive. The models showed a good fit in 
tracking the capacitances' variation almg a 
resistive load line of an actual 0.15 pm GaAs 
device, Good agreement between the simulated 
and measured results of a MMIC frequency 
tripler is also obtained by incorporating the 
proposed capacitance models in the circuit 
simulation. 
REFERENCES 
[I] David E. Root and Brian Hughes, "Princ:iples of 
Nonlinear Active Device Modeling for Circuit 
Simulation," 1988, Proc. 32"d IEEE MTT ARFTG 
Conference, Tempe, AZ, pp. 3-26. 
[2] 
Large-Signal Extraction Techniques for Heterojum d o n  
FET's," IEEE Trans. Microwave Theory and Tech., Vol. 
Ph. Jansen et al., "Consistent Small-Signal and 
I"IT-43, NO. 1, pp. 87-93, 1995. 
[3] 
Determining the FET Small-Signal Equivalent Circuit," 
IEEE Trans. Microwave Theory Tech., vol. 36, no. 7, pp. 
Gilles Dambrine et al., "A New Method for 
1151-1159, Jul. 1988. 
Expressions for modeling the capacitances' 
variation along resistive load line in the IV plane 
of the HEMT have been proposed. The 
Cgd I Cgdo 1 Cgdp I Cgdn I ra  I r4) I r50 I r5 1 
5-Ohm 1 12.9 I 0.8 I 8.5 I 11.4 I 4.7 I 13.7 I 3.6 
Table 1. Fitted models for Cgs and Cgd along a 5-Ohm resistive load line. 
1388 


Empirical load-line capacitance models for HEMT

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Empirical load-line capacitance models for HEMT

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