Nano Transistor represents a unique system for exploring physical phenomena pertaining to charge transport at the nano scale and is expected to play a critical role in future evolution of electronic and optoelectronic devices. This paper summarizes some of the essential electrostatics of nano Metal Oxide Semiconductor Field effect Transistor (MOSFET) and their electrical properties. Though the general focus of
this work is on surface potential yet the first part presents a brief discussion of the independence of charge at the top of the barrier in the channel of MOS Transistor on Drain voltage. The quantum capacitance is discussed at length. The superposition
theorem is used, thereafter, to obtain an expression for self consistent potential in the channel. Finally the I-V characteristics of the device are explored using Landauer
formalism. The simulated results for a device are observed to represent the realistic behaviour of the device.
When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2212

Singh, Lalit

Tyag, B.P.

SocioEconomic Challenges Journal (Sumy State University)

 
 
 
J. Nano- Electron. Phys. 
3 (2011) No1, P. 808-813 
Ó 2011 SumDU 
(Sumy State University) 
 
 
808 
PACS number: 85.30 De 
 
ELECTROSTATICS OF SILICON NANO TRANSISTOR 
 
Lalit Singh, B.P. Tyag 
 
 Department of Physics, D B S (Post Graduate) College, 
 Dehradun – 248001, India 
 E-mail: lalitrawat02@gmail.com  
 
Nano Transistor represents a unique system for exploring physical phenomena 
pertaining to charge transport at the nano scale and is expected to play a critical role 
in future evolution of electronic and optoelectronic devices. This paper summarizes 
some of the essential electrostatics of nano Metal Oxide Semiconductor Field effect 
Transistor (MOSFET) and their electrical properties. Though the general focus of 
this work is on surface potential yet the first part presents a brief discussion of the 
independence of charge at the top of the barrier in the channel of MOS Transistor on 
Drain voltage. The quantum capacitance is discussed at length. The superposition 
theorem is used, thereafter, to obtain an expression for self consistent potential in the 
channel. Finally the I-V characteristics of the device are explored using Landauer 
formalism. The simulated results for a device are observed to represent the realistic 
behaviour of the device. 
 
Keywords: NANOSCALE MOSFET, OPTOELECTRONICS, ELECTROSTATICS, 
QUANTUM CAPACITANCE AND LANDAUER FORMALISM. 
 
(Received 04 February 2011) 
 
1. INTRODUCTION 
 
A substantial  progress  in Integrated circuit  technology is  primarily  due to  
downscaling trends of Metal Oxide Semiconductor Field Effect Transistor 
(MOSFET) that have continued even to the present day [1, 2]. Recently, 
various semiconductor nanowire (NW) devices have drawn considerable 
attention because of their possible applications in future electronics and 
optoelectronics.  Continued  MOSFET  scaling  has  led  to  the  study  of  non  
planer FET geometries that can provide better short-channel control than 
conventional planer FETs [3-6]. In particular, gate-all-around (GAA) or 
surround-gate (SG) FETs with thin nanowire channel can provide superior 
electrostatic characteristics that will allow continued scaling beyond what is 
possible with planer technology [3, 15]. Quantum confinement effects make 
modelling of nanowire (NW) transistors a complex problem [12, 14]. While 
there are many studies in the literature on the modelling of nanowire 
transistors based on Non Equilibrium Greens’ Function or Monte Carlo 
approach [5, 16]. The physics related to the operation of nanowire 
transistors need to be well articulated. Ballistic Transport and realistic sub 
band parameters can be developed for circuit design using simulation 
programme with integrated circuit emphasis like simulations. Among the 
different materials considered for growing nano material (nanowire), Si has 
been studied extensively due to its compatibility with conventional Si CMOS 
technology [13]. 
 
 
 
 ELECTROSTATICS OF SILICON NANO TRANSISTOR 809 
2. THEORY 
 
Natori proposed the model for MOSFET in the ballistic regime [7]. In his 
model,  there  are  two  important  simplifications  that  were  made.  1.  We  
neglected 2-D electrostatics, which is important in short-channel MOSFETs. 
2. We assumed that above threshold the charge at the top of the barrier is 
approximately independent of drain bias. Now we will discuss these two 
issues here separately [9]. 
 
2.1 Role of Quantum Capacitance  
 
The MOS electrostatics is most important thing to understand about the 
MOSFET. Fig. 1(a) shows the energy diagram. We see that the positive 
voltage at the gate, which lower the charge carrier’s energy and bends the 
band down by an amount qψs,  appears  partially  across  the oxide layer  and 
partly across the depletion region of the semiconductor [10]. 
 
'
G S oxV Vy= + , 
 
where 'G G FBV V V= -  and VFB is  flat  band  Voltage.  The  voltage  across  the  
oxide is obviously related to the charge on either side, divided by 
capacitance. Hence, 
 
( )x sox
OX
ox OX
QQt
V
C
y
e
--= = , 
 
where permittivity of the oxide (SiO2) and COX is the oxide layer capacitance 
per unit area. Hence equation (1) may be written as, 
 
 
'
2
'
( )
( )
ns i
G
OX
s
i G
OX
q E o
V
C q
q n
E o qV
C
= -
= - +
 (1) 
 
Here, q is the energy of charge carrier at the top of the barrier. That gives 
us the information about Self Consistent Potential (USLF). We will solve the 
expression for it in next section. Here, we will solve modified one-
dimensional (1-D) Poisson equation for the surface potential [14]. 
 
( ) ( )2
2 2
S GS bis
si
y V V yd
e
dy
y ry
el
æ ö- -- = -ç ÷ç ÷è ø
 
 
Here, 
2
lnB A Dbi
i
K T N N
V
q n
æ ö= ç ÷
è ø
 is built in potential of p-n junctions between the 
Source/Drain and channel under flat band condition while at threshold it 
becomes lnB Dbi
A
K T N
V
q N
æ ö= ç ÷
è ø
: The geometrical scaling length si si ox
ox
t tel e=  
 
 
 
810 LALIT SINGH, B.P. TYAG  
 
 
Fig. 1 – Conduction band energy vs. position in the bulk silicon at equilibrium (a) 
and Capacitor model for 2-D electrostatic (b) 
 
provides a measure how effectively the gate potential (VG), modulate the 
surface potential ys. Semiconductor capacitance [9], (above threshold) 
 
 . s is inv
s s
dQ dQ
C C
d dy y= - = - = . 
 
This is closely related to quantum capacitance and become important as 
device enters into nanoscale (thickness of oxide layer tending towards zero). 
Under such circumstances the above expression for quantum capacitance 
reduces to [9], 
 
 
( )
.
. 2
2 2
0
s
s
s
s D D f
s
qdn
C
d
f
C q N dE q N E
y
y
¥
= -
¶= = á ñ
¶ò
 (2) 
 
where the 2-D density of state 22 DiD
m sN p= h and Dim  is the density of state 
effective mass. This reveals that the quantum capacitance depends on the 
average 2-D density of state at Fermi level. The charge at the top of the 
barrier is also related to the potential to the potential at the top of the 
barrier [9]. 
 
 
-+ += nnn  (3) 
 
 ( ) ( )2 2
2 2
D D
o F o F D
N N
n F F qVh h= + -  (4) 
 
According to this model, change in gate potential produces a change in 
surface potential. And this can be written as, 
 
 
 
 
 ELECTROSTATICS OF SILICON NANO TRANSISTOR 811 
 1 1
G
S OX
q V
E
C C
dd = - +  (5) 
 
Here Cs is quantum capacitance or surface capacitance. 
 
2.2 2-D Electrostatics  
 
In this section we will examine the self-consistent potential by considering a 
MOSFET  is  regarded  as  a  three  capacitor  as  shown  in  fig.  1(b),  which  is  
generally evaluated by the external voltage and charge in the channel. Hence 
by superposition theorem, the self-consistent potential, is USLF = UL + UP, 
where first term is the solution of Laplace equation by assuming that there 
is no charge carrier is present in the channel and second is the solution of 
Poisson equation in the presence of charge in the channel. Solution of 
Laplace equation is, 
 
( )L G G D D S SGU q V V Va a a= - + +  
 
where G GC Ca å= , D DC Ca å= , S SC Ca å= , DC , GC  and SC  refer to the three 
capacitors that describe the electrostatics control of the three electrodes. Solu-
tion of Poisson equation is, 2P sU q n Cå= , Hence complete potential will be, 
 
( )
2
s
SLF G G D D S SG
q nU q V V V
C
a a a
S
= - + + +
 
 
3. ELECTRONIC TRANSPORT 
 
For the calculation of drain current through the nano MOS Transistor we 
employ the Landauer formalism. This is widely used to evaluate the current 
in a situation for which quantum mechanical tunneling dominates. That is 
drain current is,  
 
( )L R R LI I I® ®= -  
 
 '
2
[ ( ) ( ) ( ) ( )]n L FL n R FR
q
I T E f E E T E f E E dE
h
= - - - -åò  (6) 
 
For elastic scattering T(E) = T(EF), 
And for the approximation ( ) ( ) ( )L FL R FR Dff E E f E E qVE
¶- - - » -
¶
 the final 
result for current is, 
 
 
2
1
2
( )
M
n F D
n
q
I T E V
h =
= - å  (7) 
where MV = no. Of transverse modes and T(EF) is average transmission 
coefficient at Fermi energy. 
 
 
 
 
812 LALIT SINGH, B.P. TYAG  
 
 
 
 
Fig. 2 – Relative charge density, ND (VD)/ND (VD = 0)  versus  Drain  voltage  (a),  
Drain voltage versus drain current (b), Carrier charge density versus gate voltage (c) 
 
4. RESULTS & DISCUSSIONS 
 
A number of modelling and simulation has been carried out on the D-G 
MOSFET geometry using 10 nm. Source-Drain extension (channel length) 
and different gate lengths with 1.5 nm silicon die oxide layers [8]. A 
hierarchy of models with increasing interest in this field is to be present 
some  Analytical  results  that  illustrate  the  capability  of  the  work.  The  
present model is an idealised structure. For calculation, the length of the 
source, channel and drain regions are all equal. The gate material is ideal n+ 
polysilicon whose work function is  equal  to  the conduction band edge.  The 
drain and the source region are uniformly doped and the channel region is 
intrinsic having length 10nm. The oxide thickness is 1.5 nm for both top 
and bottom gates, and the silicon film thickness is 3.6 nm. The transverse 
effective mass mt = 0.19 mo (mass  in  x-y  pane  i.e.  mx-y) and ml = 0.91 mo  
(mass in z pane i.e. mz), threshold voltage, VT = EF/q = 0.2 V. Fig. 2(b) shows 
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
VG=0.5V
D
ra
in
 C
ur
re
nt
(m
A)
Drain Voltage(V)
VG=0.4V
b
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0.0
0.2
0.4
0.6
0.8
1.0
 n
D
(V
D
)/n
D
(V
D
=0
)
Gate Voltage(V)
a 
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.0
0.5
1.0
1.5
2.0
2.5
C
ar
rie
r C
ha
rg
e 
D
en
si
ty
(n
i)
Gate voltage (v) 
     c 
 
 
 
 ELECTROSTATICS OF SILICON NANO TRANSISTOR 813 
the variation of calculated drain current (ID) as a function of drain voltage at 
a different gate voltage (i.e. at VG = 0.3V and VG = 0.4V) for common source 
characteristics at room temperature. Fig. 2(a) is the plot of computed 
nD(VD)/nD (VD = 0) versus VD. This revels that carrier density is approxi-
mately same as Drain Voltage varies. Let us consider the solution of equation 
first  and  fourth  for  two  cases:  -  First,  assume  COX is small, than a small 
change in ns has a large effect on Ei(0), according to first equation. Now on 
increasing drain voltage, ns will decreases according to (4).But according to 
equation (1) ns will, in turn, decrease Ei(0). But again equation (4) revels that 
smaller El(o) will increase ns.Hence this feedback mechanism keeps ns fixed 
with drain bias. For large COX equation (1) shows that El(0) will be set 
directly  by  the  gate  voltage.  From  above  discussion,  we  consider  that  for  
small COX, the gate voltage controls the potential of the top of the barrier. 
 
5. CONCLUSIONS  
 
In this study, the electrostatics of nano transistor has been investigated by 
considering the 2-D electrostatics and quantum capacitance. We conclude that 
the Si/SiO2 interface, that trap mobile charge carriers and cause a potential or 
even a full depletion of MOS Transistor, strongly influence the electrical 
properties of nano transistor. Simple formulas to estimate the self-Consistent 
Potential, Quantum capacitance hence current have been presented. 
 
REFERENCES 
1. Y. Yamada, H. Tsuchiya, M. Ogawa, IEEE T. Electron. Dev. 56, 1396 (2009). 
2. R. Zhibin, R. Venugopal, S. Goasguen, S. Datta, M.S. Lundstrom, IEEE T. Electron. 
Dev. 50, 1914 (2003). 
3. P. Michetti, G. Mugnaini, G. Iannaccone, IEEE T. Electron. Dev. 56, 1402 (2009). 
4. F. Assad, R. Zhibin, D. Vasileska, S. Datta, M. Lundstrom, IEEE T. Electron. 
Dev. 47, 232 (2000). 
5. M. Lenzi, P. Palestri, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, 
G. Baccarani, IEEE T. Electron. Dev. 55, 2086 (2008). 
6. E. Lind, M.P. Persson, Y.-M. Niquet, IEEE T. Electron. Dev. 56, 201 (2009). 
7. Kenji Natori J. Appl. Phys. 76, 4879 (1994). 
8. M.S. Lundstrom, Z. Ren, IEEE, T. Electron. Dev. 49, 133 (2002). 
9. Mark S. Lundstrom, Nanoscale Transistors Device Physics Modelling and Simu-
lation, (Springer). 
10. S.M. Sze, Semiconductor Devices: Physics and Technology (Wiley, New York, 1985). 
11. A. Rahman, G. Jing, S. Datta, M.S. Lundstrom, IEEE T. Electron. Dev. 50, 1853 
(2003). 
12. John D. Millers, A Hand Book of Nano Physics (Dominant Publishers). 
13. W. Lu, Ch.M. Lieber, J. Phys. D.: Appl. Phys. 39, R387 (2006).  
14. Zh. Yun, C. Rivas, R. Lake, K. Alam, T.B. Boykin, G. Klimeck, IEEE T. 
Electron. Dev. 52, 1097 (2005). 
15. E. Gnani, S. Reggiani, M. Rudan, G. Baccarani, J. Comput. Electron. 4, 71 (2005). 
16. L. Lucci, Solid State Trans. 19, 9 (2001). 
17. ITRS Origination, International Technology Roadmap for Semiconductor Report-
2007 Edition (2007). 


Electrostatics of silicon nano transistor

Electronic Sumy State University Institutional Repository

   J. Nano- Electron. Phys. 3 (2011) No1, P. 808-813 Ó 2011 SumDU (Sumy State University)   808 PACS number: 85.30 De  ELECTROSTATICS OF SILICON NANO TRANSISTOR  Lalit Singh, B.P. Tyag   Department of Physics, D B S (Post Graduate) College,  Dehradun – 248001, India  E-mail: lalitrawat02@gmail.com   Nano Transistor represents a unique system for exploring physical phenomena pertaining to charge transport at the nano scale and is expected to play a critical role in future evolution of electronic and optoelectronic devices. This paper summarizes some of the essential electrostatics of nano Metal Oxide Semiconductor Field effect Transistor (MOSFET) and their electrical properties. Though the general focus of this work is on surface potential yet the first part presents a brief discussion of the independence of charge at the top of the barrier in the channel of MOS Transistor on Drain voltage. The quantum capacitance is discussed at length. The superposition theorem is used, thereafter, to obtain an expression for self consistent potential in the channel. Finally the I-V characteristics of the device are explored using Landauer formalism. The simulated results for a device are observed to represent the realistic behaviour of the device.  Keywords: NANOSCALE MOSFET, OPTOELECTRONICS, ELECTROSTATICS, QUANTUM CAPACITANCE AND LANDAUER FORMALISM.  (Received 04 February 2011)  1. INTRODUCTION  A substantial  progress  in Integrated circuit  technology is  primarily  due to  downscaling trends of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that have continued even to the present day [1, 2]. Recently, various semiconductor nanowire (NW) devices have drawn considerable attention because of their possible applications in future electronics and optoelectronics.  Continued  MOSFET  scaling  has  led  to  the  study  of  non  planer FET geometries that can provide better short-channel control than conventional planer FETs [3-6]. In particular, gate-all-around (GAA) or surround-gate (SG) FETs with thin nanowire channel can provide superior electrostatic characteristics that will allow continued scaling beyond what is possible with planer technology [3, 15]. Quantum confinement effects make modelling of nanowire (NW) transistors a complex problem [12, 14]. While there are many studies in the literature on the modelling of nanowire transistors based on Non Equilibrium Greens’ Function or Monte Carlo approach [5, 16]. The physics related to the operation of nanowire transistors need to be well articulated. Ballistic Transport and realistic sub band parameters can be developed for circuit design using simulation programme with integrated circuit emphasis like simulations. Among the different materials considered for growing nano material (nanowire), Si has been studied extensively due to its compatibility with conventional Si CMOS technology [13].     ELECTROSTATICS OF SILICON NANO TRANSISTOR 809 2. THEORY  Natori proposed the model for MOSFET in the ballistic regime [7]. In his model,  there  are  two  important  simplifications  that  were  made.  1.  We  neglected 2-D electrostatics, which is important in short-channel MOSFETs. 2. We assumed that above threshold the charge at the top of the barrier is approximately independent of drain bias. Now we will discuss these two issues here separately [9].  2.1 Role of Quantum Capacitance   The MOS electrostatics is most important thing to understand about the MOSFET. Fig. 1(a) shows the energy diagram. We see that the positive voltage at the gate, which lower the charge carrier’s energy and bends the band down by an amount qψs,  appears  partially  across  the oxide layer  and partly across the depletion region of the semiconductor [10].  'G S oxV Vy= + ,  where 'G G FBV V V= -  and VFB is  flat  band  Voltage.  The  voltage  across  the  oxide is obviously related to the charge on either side, divided by capacitance. Hence,  ( )x soxOXox OXQQtVCye--= = ,  where permittivity of the oxide (SiO2) and COX is the oxide layer capacitance per unit area. Hence equation (1) may be written as,   '2'( )( )ns iGOXsi GOXq E oVC qq nE o qVC= -= - + (1)  Here, q is the energy of charge carrier at the top of the barrier. That gives us the information about Self Consistent Potential (USLF). We will solve the expression for it in next section. Here, we will solve modified one-dimensional (1-D) Poisson equation for the surface potential [14].  ( ) ( )22 2S GS bissiy V V ydedyy ryelæ ö- -- = -ç ÷ç ÷è ø  Here, 2lnB A DbiiK T N NVq næ ö= ç ÷è ø is built in potential of p-n junctions between the Source/Drain and channel under flat band condition while at threshold it becomes lnB DbiAK T NVq Næ ö= ç ÷è ø: The geometrical scaling length si si oxoxt tel e=     810 LALIT SINGH, B.P. TYAG    Fig. 1 – Conduction band energy vs. position in the bulk silicon at equilibrium (a) and Capacitor model for 2-D electrostatic (b)  provides a measure how effectively the gate potential (VG), modulate the surface potential ys. Semiconductor capacitance [9], (above threshold)   . s is invs sdQ dQC Cd dy y= - = - = .  This is closely related to quantum capacitance and become important as device enters into nanoscale (thickness of oxide layer tending towards zero). Under such circumstances the above expression for quantum capacitance reduces to [9],   ( ).. 22 20ssss D D fsqdnCdfC q N dE q N Eyy¥= -¶= = á ñ¶ò (2)  where the 2-D density of state 22 DiDm sN p= h and Dim  is the density of state effective mass. This reveals that the quantum capacitance depends on the average 2-D density of state at Fermi level. The charge at the top of the barrier is also related to the potential to the potential at the top of the barrier [9].   -+ += nnn  (3)   ( ) ( )2 22 2D Do F o F DN Nn F F qVh h= + -  (4)  According to this model, change in gate potential produces a change in surface potential. And this can be written as,      ELECTROSTATICS OF SILICON NANO TRANSISTOR 811  1 1GS OXq VEC Cdd = - +  (5)  Here Cs is quantum capacitance or surface capacitance.  2.2 2-D Electrostatics   In this section we will examine the self-consistent potential by considering a MOSFET  is  regarded  as  a  three  capacitor  as  shown  in  fig.  1(b),  which  is  generally evaluated by the external voltage and charge in the channel. Hence by superposition theorem, the self-consistent potential, is USLF = UL + UP, where first term is the solution of Laplace equation by assuming that there is no charge carrier is present in the channel and second is the solution of Poisson equation in the presence of charge in the channel. Solution of Laplace equation is,  ( )L G G D D S SGU q V V Va a a= - + +   where G GC Ca å= , D DC Ca å= , S SC Ca å= , DC , GC  and SC  refer to the three capacitors that describe the electrostatics control of the three electrodes. Solu-tion of Poisson equation is, 2P sU q n Cå= , Hence complete potential will be,  ( )2sSLF G G D D S SGq nU q V V VCa a aS= - + + +  3. ELECTRONIC TRANSPORT  For the calculation of drain current through the nano MOS Transistor we employ the Landauer formalism. This is widely used to evaluate the current in a situation for which quantum mechanical tunneling dominates. That is drain current is,   ( )L R R LI I I® ®= -    '2[ ( ) ( ) ( ) ( )]n L FL n R FRqI T E f E E T E f E E dEh= - - - -åò  (6)  For elastic scattering T(E) = T(EF), And for the approximation ( ) ( ) ( )L FL R FR Dff E E f E E qVE¶- - - » -¶ the final result for current is,   212( )Mn F DnqI T E Vh == - å  (7) where MV = no. Of transverse modes and T(EF) is average transmission coefficient at Fermi energy.     812 LALIT SINGH, B.P. TYAG      Fig. 2 – Relative charge density, ND (VD)/ND (VD = 0)  versus  Drain  voltage  (a),  Drain voltage versus drain current (b), Carrier charge density versus gate voltage (c)  4. RESULTS & DISCUSSIONS  A number of modelling and simulation has been carried out on the D-G MOSFET geometry using 10 nm. Source-Drain extension (channel length) and different gate lengths with 1.5 nm silicon die oxide layers [8]. A hierarchy of models with increasing interest in this field is to be present some  Analytical  results  that  illustrate  the  capability  of  the  work.  The  present model is an idealised structure. For calculation, the length of the source, channel and drain regions are all equal. The gate material is ideal n+ polysilicon whose work function is  equal  to  the conduction band edge.  The drain and the source region are uniformly doped and the channel region is intrinsic having length 10nm. The oxide thickness is 1.5 nm for both top and bottom gates, and the silicon film thickness is 3.6 nm. The transverse effective mass mt = 0.19 mo (mass  in  x-y  pane  i.e.  mx-y) and ml = 0.91 mo  (mass in z pane i.e. mz), threshold voltage, VT = EF/q = 0.2 V. Fig. 2(b) shows 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.000.050.100.150.200.250.300.350.400.45VG=0.5VDrain Current(mA)Drain Voltage(V)VG=0.4Vb0.0 0.1 0.2 0.3 0.4 0.5 0.60.00.20.40.60.81.0 nD(VD)/nD(VD=0)Gate Voltage(V)a 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.00.51.01.52.02.5Carrier Charge Density(ni)Gate voltage (v)      c     ELECTROSTATICS OF SILICON NANO TRANSISTOR 813 the variation of calculated drain current (ID) as a function of drain voltage at a different gate voltage (i.e. at VG = 0.3V and VG = 0.4V) for common source characteristics at room temperature. Fig. 2(a) is the plot of computed nD(VD)/nD (VD = 0) versus VD. This revels that carrier density is approxi-mately same as Drain Voltage varies. Let us consider the solution of equation first  and  fourth  for  two  cases:  -  First,  assume  COX is small, than a small change in ns has a large effect on Ei(0), according to first equation. Now on increasing drain voltage, ns will decreases according to (4).But according to equation (1) ns will, in turn, decrease Ei(0). But again equation (4) revels that smaller El(o) will increase ns.Hence this feedback mechanism keeps ns fixed with drain bias. For large COX equation (1) shows that El(0) will be set directly  by  the  gate  voltage.  From  above  discussion,  we  consider  that  for  small COX, the gate voltage controls the potential of the top of the barrier.  5. CONCLUSIONS   In this study, the electrostatics of nano transistor has been investigated by considering the 2-D electrostatics and quantum capacitance. We conclude that the Si/SiO2 interface, that trap mobile charge carriers and cause a potential or even a full depletion of MOS Transistor, strongly influence the electrical properties of nano transistor. Simple formulas to estimate the self-Consistent Potential, Quantum capacitance hence current have been presented.  REFERENCES 1. Y. Yamada, H. Tsuchiya, M. Ogawa, IEEE T. Electron. Dev. 56, 1396 (2009). 2. R. Zhibin, R. Venugopal, S. Goasguen, S. Datta, M.S. Lundstrom, IEEE T. Electron. Dev. 50, 1914 (2003). 3. P. Michetti, G. Mugnaini, G. Iannaccone, IEEE T. Electron. Dev. 56, 1402 (2009). 4. F. Assad, R. Zhibin, D. Vasileska, S. Datta, M. Lundstrom, IEEE T. Electron. Dev. 47, 232 (2000). 5. M. Lenzi, P. Palestri, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, G. Baccarani, IEEE T. Electron. Dev. 55, 2086 (2008). 6. E. Lind, M.P. Persson, Y.-M. Niquet, IEEE T. Electron. Dev. 56, 201 (2009). 7. Kenji Natori J. Appl. Phys. 76, 4879 (1994). 8. M.S. Lundstrom, Z. Ren, IEEE, T. Electron. Dev. 49, 133 (2002). 9. Mark S. Lundstrom, Nanoscale Transistors Device Physics Modelling and Simu-lation, (Springer). 10. S.M. Sze, Semiconductor Devices: Physics and Technology (Wiley, New York, 1985). 11. A. Rahman, G. Jing, S. Datta, M.S. Lundstrom, IEEE T. Electron. Dev. 50, 1853 (2003). 12. John D. Millers, A Hand Book of Nano Physics (Dominant Publishers). 13. W. Lu, Ch.M. Lieber, J. Phys. D.: Appl. Phys. 39, R387 (2006).  14. Zh. Yun, C. Rivas, R. Lake, K. Alam, T.B. Boykin, G. Klimeck, IEEE T. Electron. Dev. 52, 1097 (2005). 15. E. Gnani, S. Reggiani, M. Rudan, G. Baccarani, J. Comput. Electron. 4, 71 (2005). 16. L. Lucci, Solid State Trans. 19, 9 (2001). 17. ITRS Origination, International Technology Roadmap for Semiconductor Report-2007 Edition (2007). 

https://essuir.sumdu.edu.ua/bitstream/123456789/22127/1/Lalit.pdf

Electrostatics of silicon nano transistor

Abstract

Similar works

Full text

Available Versions

SocioEconomic Challenges Journal (Sumy State University)

Electronic Sumy State University Institutional Repository