這篇論文的主題為提出一個具有校正頻寬之9.5Gb/s全數位資料回復電路。此論文提出一種校正頻寬的機制，使得當輸入資料密度變動時頻寬固定。此全數位資料回復電路使用28奈米製程製做。晶片面積為0.065毫米平方。在電源1.05伏特下消耗的功率為33毫瓦。量測到的回復時脈方均根抖動為2.25ps。This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7
