A compatibility graph-based, general area router for integrated circuit (IC) designs is presented. The highly flexible constraint system allows a number of modern and mixed-signal routing requirements to be handled, even for a large number of nets. The IC router can efficiently construct near-minimal Steiner trees for multi-terminal nets in both classical rectilinear, or Manhattan, geometry as well as octilinear geometries. These Steiner trees can be constructed around blockages, and in the presence of obstacles such as other nets. A method for routing trees through weighted areas is also introduced. The routing system can predict congested routing areas before routing is performed, and appropriately weight congested areas in order to reduce net congestion. Finally, a fast crosstalk violation checker can run alongside the routing engine. Each portion of the router is bounded by O(n log(n)) runtime, or less, making the entire routing process bounded by the same runtime. The system thus scales well to handle a very large number of exact routes in a fully mixed-signal aware engine, in either rectilinear or newly-introduced octilinear geometries
