Structured development of an asynchronous forth processor using trace theory

Abstract

This thesis examines the use of a structured design methodology in the design of asynchronous circuits so that high level constructs can be specified purely in terms of signal exchanges and without the intrusion of lower level concepts. Trace theory is used to specify a multi-processor Forth machine at a high level then part of the design is further elaborated using trace theory operations to (insure that the behaviours of the lower level constructs will combine to give the high level specified behaviour without locking or other hazards. A novel form of threaded language to take advantage of the machine architecture is developed. At suitable points the design is tested by simulation. The stack element which is designed is reduced to an electric circuit which is itself tested by simulation to verify the design