Interconnect Testing for 3D Stacked Memories

Abstract

Three-dimensional stacked ICs (3D-SICs) technology based on Through-Silicon Vias (TSVs) provides numerous advantages as com- pared to traditional 2D-ICs. TSVs are holes going vertically through the chip silicon substrate filled with a conducting material. A potential application is a 3D-SIC where one or more memory dies are stacked on a logic die; thereby increasing the memory density, enhancing its throughput, and reducing its latency and power consumption as compared to planar ICs. However, testing the TSV interconnects between the memory and logic die is challenging, as both memory dies and logic dies might come from different manufacturers. Currently, extended versions of two 2D standards might be applicable to test these interconnects. The first (Boundary Scan Based) method extends JTAG in which Boundary Scan Cells (BSCs) are placed on both TSVs ends providing full TSV controllability and observability to the TSVs. The second (Logic Based) method that can be applied is an extended form of the IEEE 1581 standard. In this standard, interconnects are tested by bypassing the memory. In the test mode, memory outputs are a direct logic function of the inputs. Both methods, however, result in extra area overhead, inflexible, and fail to address dynamic and time-critical faults (at speed testing). In addition, memory vendors have been reluctant to put JTAG or additional DfT structures on their memory devices. In our Memory Based Interconnect Testing (MBIT) approach, we perform a post-bond memory based test where we test the interconnects by converting the developed test patterns to memory read and write operations. This method results in (1) zero area overhead, (2) the ability to detect both static fault and dynamic faults, (3) at speed testing, and (4) flexibility in applying the test patterns, as this can be executed by the CPU on the logic die.Computer EndineeringElectrical Engineering, Mathematics and Computer Scienc