Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

Abstract

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface- and thin-SOI microstructures that included microcavities, a RF switch and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses design aspects and demonstrates the encapsulation results. Encapsulation of structural area as large as 955 x 827 µm^2 has been successfully achieved.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc