Off-chip buses account for a significant portion of the total system power
consumed in embedded systems. Bus encoding schemes have been proposed to
minimize power dissipation, but none has been demonstrated to be optimal with
respect to any measure. In this paper, we give the first provably optimal and
explicit (polynomial-time constructible) families of memoryless codes for
minimizing bit transitions in off-chip buses. Our results imply that having
access to a clock does not make a memoryless encoding scheme that minimizes bit
transitions more powerful.Comment: Proceedings of the 2006 IEEE/ACM international Conference on
Computer-Aided Design (San Jose, California, November 05 - 09, 2006). ICCAD
'06. ACM, New York, NY, 369-37
