Liu, Wei

Nannarelli, Alberto

With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area

Online Research Database In Technology

Post-placement temperature reduction techniques

http://orbit.dtu.dk/ws/files/5128402/Liu.pdf

Post-placement temperature reduction techniques

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Online Research Database In Technology