Haandbæk, Niels

Isager, Mogens

Nielsen, Lars Skovby

Paker, Ozgun

Sparsø, Jens

This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications

Online Research Database In Technology

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

http://orbit.dtu.dk/ws/files/4374798/Paker.pdf

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

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Online Research Database In Technology