Madsen, Jan

Nielsen, Sune Fallgaard

We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle constraints. Our approach eliminates the large power spikes, resulting in an increased battery lifetime, a property of utmost importance for battery powered embedded systems. Our approach extends the partial-clique partitioning algorithm by introducing power awareness through a heuristic algorithm which bounds the design space to those of power feasible schedules. We have applied our algorithm on a set of dataflow graphs and investigated the impact on circuit area when applying different power constraints

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Downloaded from orbit.dtu.dk on: Dec 17, 2017Power Constrained High-Level Synthesis of Battery Powered Digital SystemsNielsen, Sune Fallgaard; Madsen, JanPublished in:DATE 2003Publication date:2003Document VersionPublisher's PDF, also known as Version of recordLink back to DTU OrbitCitation (APA):Nielsen, S. F., & Madsen, J. (2003). Power Constrained High-Level Synthesis of Battery Powered DigitalSystems. In DATE 2003 (pp. 1136-1137). IEEE.Power Constrained High-Level Synthesisof Battery Powered Digital SystemsS.F. Nielsen and J. MadsenInformatics and Mathematical ModellingTechnical University of Denmark{sfn,jan}@imm.dtu.dkAbstractWe present a high-level synthesis algorithm solving thecombined scheduling, allocation and binding problem min-imizing area under both latency and maximum power perclock-cycle constraints. Our approach eliminates the largepower spikes, resulting in an increased battery lifetime, aproperty of outmost importance for battery powered em-bedded systems. Our approach extends the partial-cliquepartitioning algorithm of [3] by introducing power aware-ness through a heuristic algorithm which bounds the designspace to those of power feasible schedules. We have appliedour algorithm on a set of dataﬂow graphs and investigatedthe impact on circuit area when applying different powerconstraints.1. IntroductionOur target applications are low-cost portable embeddedsystems. Today, consumers demand portable applicationsso tiny that they go virtually undetected when not in use.An interesting aspect of this application area is the low-cost issue which puts focus on reducing the overall systemcost, eg. a requirement to select a low-priced (low-quality)battery over a high-priced (high-quality) battery. Now, theamount of total energy/charge available from a battery, andthus its life-time, depends strongly on the current proﬁleof the application [1, 2]. In particular if the peak-currentexceeds a maximum-threshold the life-time starts droppingdramatically, this effect is more dominant on batteries oflow quality, where up to a 20-30 percent extension of life-time has been reported when designing for battery poweredsystems [1]. In ﬁgure 1 is shown both an undesirable and amore desirable schedule.So far the main efforts in low-power synthesis can bedivided into two groups: (a) Low level allocation and as-signment [4, 5, 6, 7]: Here the goal is to combine func-tional units and operations in such a way that the internal<P<PTTtPFigure 1. Undesired power schedule (top).Desired power schedule (bottom).switching activity of the functional units is minimized. (b)Task level scheduling [1, 2, 8]: Here the goal is to sched-ule tasks in such an order the peak system power is min-imized. The majority of these algorithms are either basedon meta-heuristic algorithms, or two-step algorithms [1, 2]where in step one a traditional time constrained scheduleis constructed and in step two the schedule is reordered tomeet the power constraint.In this paper we present a heuristic synthesis algorithmwhich solves: (i) scheduling, (ii) allocation and (iii) as-signment simultaneously under both a time and power con-straint. This enables us to expand the exploration of thedesign space to include different types of functional unitseg. the speed and energy usage of an operator can be tradedversus the area of the operator.2. Power Heuristic SchedulingThe main idea of our algorithm is to heuristically“stretch” the classical asap schedule to ﬁt the power con-straint, ie. to schedule the operators as fast as possible, butonly if there is power available meaning some operatorswillbe delayed additional cycles. The power constrained asapProceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE’03) 1530-1591/03 $17.00 © 2003 IEEE Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:36:31 EST from IEEE Xplore.  Restrictions apply. Module Oprs Area Clk-cyc. Padd {+} 87 1 2.5sub {−} 87 1 2.5comp {>} 8 1 2.5ALU {+,−, >} 97 1 2.5Mult (ser.) {∗} 103 4 2.7Mult (par.) {∗} 339 2 8.1input imp 16 1 0.2output xpt 16 1 1.7Table 1. Functional unit library.scheduling algorithm, pasap (P<), is as follows:Initialize: Schedule source start-time to zero and initializethe execution offset oi (cycles) to zero for all operators.step 1: Pick an unscheduled operator vistep 2: If vi has unscheduled predecessors, goto 4.step 3: if there is power available in the execution time in-terval [(ti+oi)..(ti+oi+di)], where di is the executiondelay of vi and ti = max{tj+dj} ∀vj → vi, scheduleoperation i at time ti, otherwise increase oi by one.step 4: If unscheduled operators, goto step 1.We have enhanced the formulation of a valid “time-extendend compatibility graph” (V 1) in [3] to includepower constraints using the pasap and its time-revesedpalap algorithms. Then the solution to the synthesis prob-lem with the minimum area and using least interconnect isthe problem of ﬁnding the Partial minimal cost clique par-titioning of V 1 which does not violate the power con-straint. As in [3] we will heuristically solve the cliquepartitioning problem, through a greedy approach ie. eval-uate the V 1 graph and pick a “best” decision, which is thenscheduled, allocated and assigned and then repeat the pro-cess until no operators are left. During this we need to en-sure feasibility, as pasap and palap are heuristic algorithmsthey depend on what operators have been scheduled, there-fore a sequence of assignments might cause the deletion ofunscheduled operators, causing an invalid schedule. Thesolution is to backtrack one step and lock the start time ofall unscheduled operators to the pasap schedule (which wasvalid) and then continue.We have benchmarked the algorithm on some CDFGs,where we have investigated the area of the resulting circuitsas a function of time and power constraints. The results areshown in ﬁgure 2. The FU library used in the tests is shownin table 1.3. ConclusionIn this paper we have presented an algorithm for time andpower constrained synthesis of digital circuits. We have ap-plied the algorithm on the traditional synthesis benchmark0 50 100 1505001000150020002500300035004000PowerAreahal (T=10) hal (T=17)cosine (T=12)cosine (T=15)cosine (T=19)elliptic (T=22) Figure 2. Power vs. area under different timeconstraints for our CDFGs.sets and investigated different regions in the time-power-constraint space. For our benchmarks we have found thatwe are able to trade in a small amount of area to obtain asolution which ﬁts our power requirements.References[1] J. Luo and N. K. Jha. Battery-Aware Static Scheduling forDistributed Real-time Embedded Systems. In proceedingsof 38th Design Automation Conference, 2001. Page(s): 444-449.[2] K.Lahiri, A. Raghunathan, S. Dey. Communication Archi-tecture Based Power Management for Battery Efﬁcient Sys-tem Design. In proceedings of Design, Automation and Testin Europe. 2002. Page(s): 691 -696[3] J. Jou; S. Kuang; R. Chen. Clique Partitioning Based Inte-grated Architecture Synthesis for VLSI Chips. In proceed-ings of International Symposium on VLSI Technology, Sys-tems, and Applications, 1993, Page(s): 58 -62.[4] Y. Choi and T. Kim. An Efﬁcient Low-Power Binding Algo-rithm in High-Level Synthesis. Circuits and Systems, 2002.ISCAS 2002. IEEE International Symposium on , Volume:4 , 2002 Page(s): 321 -324.[5] M. S. Bright and T. Arslan. Synthesis of Low-PowerDSP Systems Using a Genetic Algorithm. In IEEE Trans-actions on Evolutionary Computation, vol. 5, no. 1, Feb2001.Page(s): 27 -40.[6] F. Gruian and K. Kuchcinski. Operator Binding andScheduling for Low Power Using Constraint Logic Pro-gramming. Euromicro Conference, 1998. Proceedings. 24th, Volume: 1 , 1998 Page(s): 83 -90 vol.1.[7] M. Bhardwaj, R. Min, A. Chandrakasan. Power-Aware Sys-tems. Very Large Scale Integration (VLSI) Systems, IEEETransactions on , Volume: 9 Issue: 6 , Dec. 2001 Page(s):757 -772.[8] J. Liu, P. H. Chou, N. Bagherzadeh, F. Kurdahi. Power-Aware Scheduling under Timing Constraint for Mission-Critical Embedded Systems. In proceedings of the 38th De-sign Automation Conference, 2001. Page(s): 840 -845.2Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE’03) 1530-1591/03 $17.00 © 2003 IEEE Authorized licensed use limited to: Danmarks Tekniske Informationscenter. Downloaded on February 24,2010 at 04:36:31 EST from IEEE Xplore.  Restrictions apply. 

Power Constrained High-Level Synthesis of Battery Powered Digital Systems

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Power Constrained High-Level Synthesis of Battery Powered Digital Systems

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