'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
A two-stage amplifier, operational at 0.8V and drawing 7/spl mu/A, has been integrated in a standard digital 0.18/spl mu/m CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with g/sub m/ control. The efficient rail-to-rail output stage is biased in class AB. The measured DC gain of the amplifier is 75dB, and the unity-gain frequency is 870kHz with a 12pF, 100k/spl Omega/load. Both input and output stage transistors are biased in weak inversion