Bjerregaard, Tobias

Sparsø, Jens

Stensgaard, Mikkel Bystrup

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A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular syste

Online Research Database In Technology

http://orbit.dtu.dk/ws/files/3880178/Bjerregaard.pdf

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

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Online Research Database In Technology