A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible

Fukaya N

Miyake H

Okabe Yoichi

Sugano T

岡部 洋一

UTokyo Repository

578 IEEE TRANSACTIONS ON MAGNETICS, VOL. MAG-21, NO. 2, MARCH 1985 
PROPOSAL  OF  UNILATERAL  SINGLE-FLUX-QUANTUM  LOGIC  GATE 
H.Miyake,  N.Fukaya,  Y.Okabe  and  T.Sugano 
Department of Electrical  and  Electronic  Engineering, 
the  University of Tokyo 
3-1 Hongo 'Ichome,  Bunkyo-ku,  Tokyo 113, Japan 
Abstract 
A new type of single  flux  quantum  logic  gate is 
proposed,  which  can  perform  unilateral  propagation of 
signal  without  using  three-phase  clock. This gate is 
designed to be  built  with  bridge-type  Josephson  junc- 
tions.  A  basic  logic  gate  consists of two  one-junction 
interferometers coupled by superconducting intercon- 
necting  lines,  and the logical states are  represented 
by  zero or one  quantized  fluxoid in one of one-junction 
interferometers. The bias  current of the  unequal  mag- 
nitude  to  each of the two one-junction  interferometers 
results in unilateral  signal flow.  By  adjusting design 
parameters  such as the  ratio of the  critical  current of 
Josephson  junctions  and  the  inductances,  circuits  with 
the  noise  immunity of greater  than 50% with  respect to 
the bias current have been designed. Three cascaded 
gates  were  modeled  and  simulated  on  a  computer, and the 
unilateral signal flow was confirmed. The simulation 
also  shows  that  a  switching  delay  about 2 picoseconds 
is feasible. 
Introduction 
In Josephson junction circuits, which  have  been 
built so far,  the  voltage  change of Josephson  junctions 
is used to represent logical states, and Josephson 
junctions  are  either  in  the  superconducting  state o 
latched in the  voltage  state  during  the  logic  cycle. 1.5 
On  t  e  other  hand  single  flux  quantum  logic  cir- 
cuits 3s'5 in which  zero or one quantized  fluxoid  in 
one-junction interferometer represents logical states 
l lOlt  or 11111 are  attractive  from  viewpoints of very  high 
switching  speed  and  extremely low power  consumption, 
because  they  can  be  built  with  bridge-type  Josephson 
junctions  having  small  capacitances  in  contrast  to  the 
conventional tunneling junctions and the Josephson 
junctions  are in the  voltage  state only for  switching 
transient. Single flux quantum logic circuits, which 
have  been  proposed so far, have  needed  a  three-phase 
clock  to  ensure  the  unilateral  propagation of  signal. 
However,  three-phase  clock  scheme  increases  the  signal 
propagation  delay  and  the  size of the gate.' 
In  this  paper, we propose  a new type of single 
flux  quantum  logic  gate  which  makes  unilateral  propaga- 
tion of signal possible without using three-phase 
clock. This circuit configuration is designed to be 
built  with  bridge-type  Josephson  junctions,  which  do 
not  have  pysteresis in their  current-voltage  charac- 
teristics,  and is expected  to  be useful as  high-speed 
logic gate because of the gmall capacitances of 
bridge-type  Josephson  junctions. 
-- Basic  Gate  Configuration 
' A basic  logic  gate  consists of two  one-junction 
interferometers coupled by superconducting intercon- 
necting lines, as  shown  in Fig. 1 (a)  and  (b), where xi 
is the  characteristic  phase of the  inductor Li given  by 
xi=211Li10/@0 . (1) 
Unilateral  propagation of signal  can  be  realized by the 
basic onfiguration shown in Fig.1  (a),  but the 
Josephson  junction J .  and  inductor  L  in  the  gate as 
illustrated in Fig.1 (b) are adaed to obtain large 
noise  immunity  with  respect  to  the  bias  'current  large, 
as will  be  mentioned  later. 
3 
Manuscript  received  September 10, 1984 
-  (b) 
Fig.1 Proposed  logic gate: J P J and J are Joseph- 
son junctions, I is the crilica3 curreat of J 
and I are  the bi& currents. (a) basic configu&th 
(b) cgnfiguration  with  large  noise  immunity. 
J I  I 
L 
Fig.2 Transmission  of  signal in the  gate  of Fig.1  (b) 
for the forward direction. (a) after J is switched, 
and  (b)  after J and J are  switched succchvely. 
3 2 
!'ig.3 Attenuation of signal  in  the  gate of Fig.1 (h) 
for  the  reverse  direction . (a) J is not  switched  by 
the  same  input  current  as in Fig.3?3(b) A  pair  of  quan- 
tized fluxoids is geneFated in the gate when larger 
current is injected  to J , but  it does not  propagate 
the pred'eeding gates th?&gh the  coupling,  because J 
is not  switched to the  voltage  state. 13 
0018-9464/85/0300-0578$01.00O1985 IEEE 
519 
The  bias currents of the  unequal  magnitude  to  each 
of the two one-junction  interferometers  results in  uni- 
lateral signal flow. Small additional input current 
given  to the left one-junction  interferometer  can  gen- 
erate  a  pair of quantized  fluxoids,  but  large  addition- 
al input  current is necessary to generate  a  pair of 
quantized fluxoids in the right one-junction inter- 
ferometer. The forward  transfer of the  quantized  flux- 
oid  from  the  left  interferometer  to  the  right  inter- 
ferometer is achieved  by  injecting  large  clockwise  cir- 
culating current into the adjacent junctions .J and 
successively  J , as shown in  Fig.2. On the  othe?  hand 
the  reverse  traisfer  from  the  right  interferometer  to 
the  left  interferometer  cannot  be  achieved,  because  the 
injected  current  through  the  coupling M2 from  the  loop 
(I) to (11) is so small that  the  Josephsan  junction  J 
cannot  be  brought  to  the  voltage  state, as shown 13 
Fig.3. 
Figure 4 (a) and (b) show  the  calculated  threshold 
characteristics of the  gate  shown  in Fig.1  (a)  and  (b) 
for the parameters listed in the figure captions, 
respectively. The threshold characteristics were ob- 
tainerf  by considering  the  stability  condition of the 
gate. The numbers in the parentheses represent the 
number of quantized  fluxoid in each  loop,  where  a  posi- 
tive  sign represents the  quantized  fluxoid  associated 
with  clockwise  circulating  current  and  a  negative  sign 
represents the quantized  fluxoid  associated  with  coun- 
terclockwise circulating current. The sum of these 
numbers  must  be zero because of the  flux  quantization 
condition  by  the  outer  superconducting  inductance  loop, 
Fig.4 Calculated threshold characteristics for the 
gate in  Fig.1  (a)  and  (b)  for the following  parameters 
values, respectively. The parameters are; (a) a$. A.= 
Fig.5 Calculated threshold characteristics in the 
phase-plane  for  the  gate  in Fig.1 (a). The parameters 
are  the  same as in  Fig. 4 (a). 
and of the  initial  condition with zero flux  quantum. 
In  the  case of the  gate shown in  Fig.1, different 
from  dc SQUID, there  exist some quantum  modes  in  the 
whole current-plane as shown in Fig.4, therefore, 
Josephson  junctions  can  not  be  in the voltage  state 
steadily  and one quantum  mode corresponds to only one 
mode in the  whole  phase-plane, as shown in  Fig.5. 
Principles of Operation 
The  principles of operation  for the gate  shown  in 
Fig.1  (b) are as follows.  Without  the  input  current I 
there is no fluxoid in any loop, or (O,O,O,O) mode! 
this  represents  logical  state r tO1t .  The input  current 
drives  the  junction  J  from  the  superconducting  state 
to the  voltage  state  and  the  voltage  induces  a  counter- 
clockwise  circulating  current  in the leftmost  loop  and 
a  clockwise  circulating  current in the adjacent.loop, 
as shown in Fig.2 (a). In consequence the current 
flowing  through  J  becomes  too small to keep the  junc- 
tion  in  the  voltag4  state  and  the junction’ J returns 
to  the  superconducting  state. It must be  notlfied that 
the  duration of’the voltage  state is so short  that the 
power  consumption  is  negligibly small and this situa- 
tion is significantly different from the latching 
operation of circuits built  with  tunnel  type  junctions. 
This clockwise  circulating  current switches J  and  J 
successively to the voltage state, resulhng in 2 
transfer’ of the quantized fluxoid to the rightmost 
loop,  or (-1,0,0,1) mode as shown in Fig.2 (b); this 
represents  logical  state “Irr. 
The,coupling between  the  basic  gates  can  be  accom- 
plished  by  mutual  inductance, or its T transform as 
shown in Fig.3. Using  the T transform  a  part of the 
clockwise  circulating  current is injected  into  the next 
gate  directry, so that  current  injection  logic  can  be 
built. Moreover, the coupling between non-adjacent 
gates  can  be  accomplished  by  connecting  the gates with 
superconducting  transmission lines as same as the vol- 
tage  mode  Josephson  junction  gates.  In this case, how- 
ever,  the  voltage  pulse  accompanied  with  the  switching 
of  the  rightmost  Josephson  junction causes the  inject- 
ing  current  into  the  next  gate to cause mode  transi- 
tion. 
Without the bias current, the gate is in the 
(O,O,O,O) mode, therefore,  resetting  the  gate to logi- 
cal state rlO1r can.be accomplished  by  reducing  the  bias 
current  to zero, similar to resetting  commonly  used  in 
Jqsephson  logic  gates  built  with tunnel junctions. In 
580 
this case, however,  Josephson  junctions  are  not in the 
voltage state, therefore,  "punchthrough"  which is in8 
herent  in tunnel type  Josephson  junction  logic  gates 
does  not  take  place. 
Design  Consideration 
Circuit  parameters,  such  as  the  ratio of the  crit- 
ical current of Josephson junctions and inductances 
were  chosen to obtain  the  largest  noise  immunity  with 
respect  to  the  bias  current  and  the  inclination AI 1 
CJ in  the  threshold  characteristics. This inclinatygn 
is related  to  the  isolation  between  the  input  and  the 
output, if it  is  large  enough,  the  change of the  phase 
difference across the  output junction.gives little  ef- 
fect  on  the  input  junction.  Unilateral  propagation of 
signal can be accomplished without J as aforemen- 
tioned,  however, in the  case of the  gate  Jhown in  Fig. 1
(a) these two parameters  are in trade-off,  therefore, 
the  maximum noise immunity  with  respect  to  the  bias 
current I obtained  with  keeping  the AI /AI as 7 is 
about 20%.B2The roll of J is  to  obtain tffz lafge  noise 
immunity with respect  to3the  bias  current  large,  keep- 
ing the AI /AI sufficiently large. If the products 
of the  cri&?calCcurrent of J With L and L are  chosen 
to be small enough with keepjng the 21 as large 
as 7, a  circulating  current  can  be ma%E noE  to flow in 
the middle two loops steadily. This means that the 
area in the  threshold  characteristics  corresponding  to 
the  modes (-l,l,O,O)  and  (-l,O,l,O), which  are not re- 
lated  to  any of the  logical state, can  be  made small 
and  the noise immunity  with  respect  to  the  bias  current 
becomes larger. Figure 4 (b) shows the calculated 
threshold  characteristics of a gate, whose  noise  immun- 
ity is larger  than 50% with  respect  to  the  bias  current 
IB2 for  large  AI /AI such as 7. 82 C' 
Thermal  Stability of Gate 
In  the  presence of the  thermal noise, it  is known 
that  thermally  actigated  switching of Josephson  junc- 
tions  may  take place. In the case of the  gate  shown  in 
Fig.1, there is only  one  potential  well  in  the  whole 
phase-plane  corresponding  to  one  quantum  mode,  and  any 
of the junctions cannot be steadily on the voltage 
state, so that  the  phases of the  junctions  are not ro- 
tating. This is different from the situation of dc 
SQUID. 
The hatched  region in Fig.4  (b) shows  the  operat- 
ing  region of the  gate  shown  in Fig.1  (b), where  only 
one  stable  point  exists in the phase-plane. With  the 
bias  current  and  input current, therefore,  the  gate  can 
be brought to (-l,O,O,l) mode. Without the input 
current,  however,  the  operating  point  is in the  over- 
lapping  region of (0.0,O.O) and  (-l,O,O,l) modes,  and 
in the  presence of thermal noise the  undesirable  mode 
transition  from (O,O,O,O) to (-l,O,O,l)  mode  may  take 
place. 
Contour maps of potential  energy  for  the gate'* 
were  calculated in  order to study  the  stability  of  the 
gate.  Figure 6 shows  the  contour  map of the  potential 
energy  in  the  overlapping  region of the two modes  for 
the parameters given in the figure caption. In this 
figure, there are two stable points at A and B 
corresponding to the mode (O,O,O,O) and (-l,O,O,l), 
respectively. The potential difference between these 
stable  points  and  the  saddle  point  at  C  is  sufficiently 
large enough to ensure that the mean time between 
failure  for  the  system  containing IO6  gates is longer 
than  one  year'  in  the  presence of the  thermal  noise  at 
4.2 K. Even  though  the  thermal  noise  at 4.2 K is con- 
sidered  in  the  design of the  operating  bias  point for 
the  gate,  the  noise  immunity  for  the  gate in  Fig.4  (b) 
is as large as 50% with  respect  to  the  bias  current 
'B2- 
(PI 
Fig.6 Contour  map of potential  energy  for  the  gate in
Fig.1 (b) , with  the  bias  current. A and B are the 
stable  points  and  C is the  saddle  point.  The  parameters 
are the same as in  Fig.2  (b),  and I -2.31 and 
I =0.71 . The  number  in  the  figure  shows  t8e 2- valu8 of 
pgtentigl  energy  in  eV  for I =50 P A .  
0 
Computer  Simulation 
Three cascaded gates shown in Fig.1 (b) were 
modeled and simulated on computer, where bridge-type 
Josephson  junctions  were  represented  with  a  resistively 
shunted  junction  model  in  the  limit of heavy  damping. 
The relevant  equations  are  for  fluxoid  quantization  in 
each  loop  and  current  continuity  at  each  node,  given  by 
the  next  eauations. 
pll+A1(sinpllt 5 @o I Gll --&+ dPll (p11-p12) 
0 3 
-A (i  +i ) = 0 1 c B1 
=O (i=1,2,3) 
-A1hl + %(asinp  (i-1) 3' @o 7 G(i-l)3 dp(i-1)3 dt 1 
(i=2,3) (5) 
I 
- A2(ic + iB2) = 0 ( 6 )  
Here, P . .  represents  the  phase  difference  .across  the 
jhh jUi%tiOn of the i gate, and G. . 'is the  parallel 
C nductance  of  the j th  %nction of thiJ ith gate,  and 
ic* igl,  and ig2 are lc/Io. I ~ ~ / I ~ ,  and I /I respec- 
tively. The existence of a fluxoid quantum B2 O in any 
one-junction  interferometer  is  represented  by  the 
change about 2n of the phase difference across the 
Josephson  junction  contained  in  that  interferometer. 
Figure 7 shows  the  results of computer simulation 
indicatmg the  forward  transfer of  a  quantized  fluxold. 
581 
lar 
Fig.7 Simulated  switching  behavior of three  cascaded 
gates,  when I is applied  to  the  input  junction of the 
first gate. Thg parameters  are  the  same as in  Fig.5. 
d p  
curred 
Fig.8 Simulated  switching  behavior of three  cascaded 
gates, when is applied to the output junction of 
the third gate?' The parameters are the same as in 
-Fig.6,,  except  for I '=2.11 C 0' 
I1 
I2 
Yl 
Ip2 
I p3  
Ip4 
2 0  
1000 
Fig.9 The  coupling  between  the  distant  gates by 
necting  with  the  superconducting  transmission  line. 
Schematic  drawing of this  coupling.  (b)  Results of 
puter  simulation of the  circuit  in (a). 
con- 
(a) 
COOm- 
when I is  applied to the  input  junction of the first 
gate. It can  be  seen that switching  delay  about 2 pi- 
coseconds per gate is feasible, when I overdrives 
about 20 percents. Figure 8 shows  the  results of com- 
puter  simulation  indicating  that  a  pair of quantized 
fluxoids is generated  in  the  third  gate,  but  it does 
not  propagate  to  the  preceeding  gates. 
Thus, the  unilaterality of signal flow was con- 
firmed  from  the  results of computer  simulation. 
Two gates  coupled  with  superconducting  transmis- 
sion  line  shown  in Fig. 9 (a) were also modeled  and 
simulated in the same way. Figure 9 (b) shows the 
results of computer  simulation  indicating  that he vol- 
tage  pulse  accompanied  with  the  switching of the output 
junction of the  first  gate  causes the injecting  current 
in  the  next  gate  to  generate  a  pair of quantized  flux- 
oids and transfer a quantized fluxoid to the right 
one-junction  interferometer. 
Conclusion 
A new type of single  flux  quantum  logic  gate  which 
can  perform  unilateral  propagation of signal has been 
designed  to  be  built  with  bridge-type  Josephson  junc- 
tions. High switching speed of 2 picoseconds is 
predicted by the computer simulation. A gate, whose 
noise  immunity is as large as 50% with  respect  to the 
bias  current  when  the  thermal noise at 4.2 K is con- 
sidered  and AI /AI  .is'as large as 7, was found  by  ad- 
justing designB$ara&eters such as the ratio of the 
critical  current of Josephson  junctions  and  inductances 
Three  cascaded  gates  were  modeled  and  simulated  on  a 
computer,  and  the  unilaterality of signal flow was con- 
firmed. 
Acknowledgement 
This  work was supported  by  the  Ministry of Educa- 
tion, Research  and  Culture under Grant-in-Aid  Y4pecial 
Promotion  Research N0.57060001~~. 
References 
1. J.Matisoo,  "Overview of Josephson  Technology  Logic 
March 1980 
and Memoryft, IBM J.  Res.  Develop.,  vol. 24, pp.113-129. 
2. T.R.Gheewala, "Josephson-Logic Devices and Cir- 
cuits", IEEE Trans. Electron Devices., vol. ED-27, 
3. H.Tamura,  Y.Okabe  and  T.Sugano, rtProposal of 
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8. E.P.Harris and W.H.Chang,  IIPunchthrough  in Josephson 
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9. T.A.Fulton and L.N.Dunkleberger, "Lifetime of the 
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10. C.D.Tesche,  "A Thermal  Activation Model. for  Noise 
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pp.119-147, 1981 


PROPOSAL OF UNILATERAL SINGLE-FLUX-QUANTUM LOGIC GATE

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PROPOSAL OF UNILATERAL SINGLE-FLUX-QUANTUM LOGIC GATE

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