IEEE = Institute of Electrical and Electronics Engineers
Abstract
金沢大学理工研究域 電子情報学系This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.Organized by the Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology Association (ECTI) Co-organized by GCEO-NGIT, Hokkaido University Technical sponsored by IEEE Circuits and Systems Society In cooperation with the Institute of Electronics, Information and Communication Engineering (IEICE
