McIntosh-Smith, Simon

Pawelczak, Grzegorz

With the expected decrease in Mean Time Between Failures (MTBF), Fault Tolerance (FT) has been identi ed as one of the major chal- lenges for exascale computing. One source of faults are soft errors caused by cosmic rays, which can cause bit corruptions to the data held in memory. Current solutions for protection against these er- rors include Error Correcting Codes (ECC), which can detect and/or correct these errors. When an error that can be detected but not corrected occurs, a Detectable Uncorrectable Error (DUE) results, and unless checkpoint-restart is used, the system will usually fail. In our work we present a probabilistic method of correcting DUEs which occur in the part of the memory where the program instruc- tions are stored. We devise a correction technique for DUEs for the ARM A64 instruction set which combines extended Hamming code with Cyclic Redundancy Check (CRC) code to provide near 100% Successful Correction Rate (SCR) of DUEs

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                          Pawelczak, G., & McIntosh-Smith, S. (2017). Correcting DetectableUncorrectable Errors in Memory. Poster session presented at SC17, Denver,United States.Publisher's PDF, also known as Version of recordLicense (if available):UnspecifiedLink to publication record in Explore Bristol ResearchPDF-documentThis is the final published version of the article (version of record). It first appeared online via Cray athttps://sc17.supercomputing.org/SC17%20Archive/tech_poster/tech_poster_pages/post174.html . Please referto any applicable terms of use of the publisher.University of Bristol - Explore Bristol ResearchGeneral rightsThis document is made available in accordance with publisher policies. Please cite only the publishedversion using the reference above. Full terms of use are available:http://www.bristol.ac.uk/pure/about/ebr-termsCorrecting Detectable UncorrectableErrors in MemoryGrzegorz Pawelczak, Simon McIntosh-SmithUniversity of BristolIntroductionWith the expected decrease in Mean Time Between Failures (MTBF), Fault Tolerance (FT)has been identified as one of the major challenges for exascale computing. One source offaults are soft errors caused by cosmic rays, which can cause bit corruptions to the data heldin memory. Current solutions for protection against these errors include Error CorrectingCodes (ECC), which can detect and/or correct these errors. When an error that can bedetected but not corrected occurs, a Detectable Uncorrectable Error (DUE) results, andunless checkpoint-restart is used, the system will usually fail. In our work we present aprobabilistic method of correcting DUEs which occur in the part of the memory where theprogram instructions are stored. We devise a correction technique for DUEs for the ARMA64 instruction set which combines extended Hamming code with Cyclic Redundancy Check(CRC) code to provide near 100% Successful Correction Rate (SCR) of DUEs.Previous WorkIn their previous work, Gottscho et al. proposed Software-Defined Error-Correcting Codes(SWD-ECC) which are capable of correcting DUEs by leveraging the properties of theunderlying ECC and the side information about the data stored [1].I Research focused on the 39-bit Single Error Correction and Double Error Detection(SECDED) code where for every 32-bits of data, an additional 7-bits of redundancy arestored to aid with error detection and correction.I In the SECDED code an occurrence of a DUE means that there are multiple candidatecodewords which are equidistant to the correct codeword.I Since all the candidate codewords are equally likely, it is impossible to determine which isthe correct one.I By assuming that the data protected is MIPS program instructions, the candidatecodewords which do not represent a valid instruction can be discarded.I This approach reduced the search space to an average of 12 valid candidate instructionsand along with an observation that some instructions are more likely than others, theywere able to correct 34% of DUEs.New Heuristic TechniquesWe extend this work by investigating the performance on the ARM A64 Instruction Setwhich similarly to MIPS uses 32-bit instructions.We introduce new heuristic techniques to reduce the number of candidate instructions inorder to improve the SCR:1. Addition of an Error Detecting Code (EDC) in order to reduce the number of candidatevalid codewords.. CRC32C is used as the EDC, where every N SECDED codewords are covered by asingle CRC32C checksum.. When a DUE occurs all valid SECDED codewords have to also produce a valid CRC32Cchecksum.. CRC32C is used because it provides a high Hamming Distance (HD) [2] and modernarchitectures, such as x86 or AMRv8a, often provide hardware support for thecomputation of the checksum via intrinsics.2. Filtering out codewords which are valid instructions, but are not deemed legal instructions.. For example a branch instruction to an invalid address is an illegal instruction andshould not be considered as a likely candidate.References[1] Mark Gottscho, Clayton Schoeny, Lara Dolecek, and Puneet Gupta.Software-Defined Error-Correcting Codes.Proceedings - 46th Annual IEEE/IFIP International Conference on DependableSystems and Networks, DSN-W 2016, pages 276–282, 2016.[2] Philip Koopman.32bitt cyclic redundancy codes for internet applications.In Proceedings of the 2002 International Conference on Dependable Systems andNetworks, DSN ’02, pages 459–472, Washington, DC, USA, 2002.[3] B Hall P Koopman, K Driscoll.Selection of Cyclic Redundancy Code and Checksum Algorithms to Ensure CriticalData Integrity.Technical report, U.S. Department of Transportation, Federal AviationAdministration, March 2015.MethodThe following heuristic approach is used to assess an instruction:* VIXL is a Runtime Code Generation Library by ARM which provides a disassembler(https://github.com/armvixl/vixl).Results & ConclusionsTo evaluate the performance of these techniques, the binary programs from the /bin/directory for the openSUSE Linux distribution are used as the training programs in order tofind the most frequent instructions, while mini-apps from the UK Mini-App Consortium(https://uk-mac.github.io/) are used as the test programs. The DUE faults areinjected by randomly selecting an instruction from the .text section of the test programand randomly flipping two unique bits in the instruction SECDED codeword.I The performance of the original method on the ARM A64 instruction set has improvedcompared to the MIPS instruction set.I The additional test for instruction legality has further reduced the number of candidateinstructions and thus improved the SCR.I The hybrid scheme of SECDED ECC and CRC32C EDC has vastly improved the SCR. TheSCR depends on the number of SECDED codewords per CRC codeword:. When N ≤ 134, this approach can correct all SECDED DUEs because the HD is 6 forCRC32C at that codeword length.. When 134 < N , the HD is 4, meaning that there is a small chance of ≈ 4.6× 10−10 [3]multiple candidate codewords, however a collision did not occur during testing.I Addition of CRC32C EDC results in no runtime overhead in this scenario, as the checksumis only ever accessed when a DUE occurs. Since instructions do not change during theexecution of the program, the checksums only ever need to be computed once.I If this approach was used for data that does change, the extra layer of CRC could createsignificant performance overhead, as Read-Modify-Writes would need to be performed toupdate the checksum.. Choosing a smaller N would improve the performance of Read-Modify-Writes.. However, the smaller the N , the higher the storage overhead. For example the storageoverheads for N = 2, N = 134 and N = 2048 are 41.03%, 0.6% and 0.04% respectively.Correcting Detectable Uncorrectable Errors in Memory https://uob-hpc.github.io/

Correcting Detectable Uncorrectable Errors in Memory

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Correcting Detectable Uncorrectable Errors in Memory

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