An architectural journey into RISC architectures for HPC workloads

Abstract

The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested