This work describes recent progress in the design, processing, upscaling, and testing of 500C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016

Beheim, Glenn M.

Chang, Carl W.

Chen, Liang-Yu

Krasowski, Michael J.

Neudeck, Philip G.

Prokop, Norman F.

Spry, David J.

NASA Technical Reports Server

National Aeronautics and Space Administration
National Aeronautics and Space Administration
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Yearlong 500 oC Operational Demonstration 
of Up-scaled 4H-SiC JFET Integrated Circuits
Philip G. Neudeck1, David J.Spry1, Michael J. Krasowski1, 
Norman F. Prokop1, Glenn M. Beheim1, Liang-Yu Chen2, and 
Carl W. Chang3
1NASA Glenn Research Center 
2Ohio Aerospace Institute
3Vantage Partners LLC
Cleveland, Ohio, USA
2018 IMAPs International Conference on High Temperature Electronics (HiTEC 2018)
9 May 2018
Albuquerque, New Mexico USA
https://ntrs.nasa.gov/search.jsp?R=20190001885 2019-08-30T22:41:49+00:00Z
National Aeronautics and Space Administration
Acknowledgements
This work was conducted by The NASA John H. Glenn Research Center in 
Cleveland, OH USA under joint funding from NASA Science Mission Directorate 
(High Operating Temperature Technology, Planetary Instrument Concepts for the 
Advancement of Solar System Observations, and Long-Lived In-Situ Solar 
System Explorer projects) and NASA Aeronautics Directorate (Transformative 
Tools and Technologies project).
HX5 Sierra (NASA Glenn)
Kelley Moses
Jose Gonzalez
Michelle Mrdenovich
Arianna Miller
Vantage Partners, LLC (NASA Glenn)
Dorothy Lukco
Carl Chang
NASA Glenn Research Center
Gary Hunter
Robert Buttler
George Ponchak
Max Scardelletti
Robert Okojie
Lawrence Greer
Félix Miranda
Lawrence Matus
Intelligent Propulsion Systems
Hybrid Electric & Turbo Electric Aircraft
SiC Electronics Benefits to NASA Missions
3
NASA GRC’s internal research effort  has been 
to focused on durable/stable integrated circuit 
operation at 500 C for > 1000 hrs.
Venus Exploration
1T. Kremic, et al., 48th Lunar and Planetary Science, 2017, 2986.
LLISSE = Long-Life In-Situ 
Solar System Explorer1
9.4 Mpa = 
92.7X Earth 
pressure + 
460 °C + 
chemical
composition
found at the
surface of
Venus (CO2, 
N2, SO2, H20, 
CO, OCS, HCl, 
HF, and H2S)
4• Normally-on 4H-SiC JFET (fabricated at NASA Glenn)
• Resistors made with same epi as channel àmatched T dependence
• Negative threshold voltage VTà negative signal voltages (0 to -10V)
• 0 V = Binary 1 (high)  -10 V = Binary 0 (low)
1M. J. Krasowski, US Patent 7,688,117 (2010).
2P. G. Neudeck, D. J. Spry, and L. Chen, Proc. IMAPS High Temperature Electronics Conf., 2016, pp. 263-271.
N-channel JFET design1,2 “Version 10.1”
NOT Logic Gate Schematic
!
National Aeronautics and Space Administration
5
SiC JFET IC Results from HiTEC 2016 
(“IC Wafer/Version 9.2”)
SEM cross-section of JFET with
two levels of metal interconnect
24-transistor ring
oscillator IC
Stable 500 °C IC operation 
for 1000’s of hours
Photo of package & chip undergoing 
650 °C oven test
Micrograph of dielectric layer crack 
feature that limits 500 °C IC lifetime
Primary design goal is extreme environment circuit durability.
6Recent Advances
(Since HiTEC 2016)
• Neudeck, et al., AIP Advances 6 (2016) 125119. 
• Neudeck, et al., IEEE Electron Device Lett. 38 
(2016) 1082-1085.
NASA SiC JFET IC operation at T > 900 °C
NASA SiC JFET IC operated immersed 
in Venus surface conditions (460 °C, 
9.4 MPa) for 3 weeks, did not fail.
7High-T packaging1,2 (32 pins, HiTEC 2016) 
1L. Chen, et al., Proc. IMAPS High Temperature Electronics Conference, 2016, pp. 66-72.
2P. G. Neudeck, et al., IEEE Electron Device Lett. 38 (2016) 1082-1085.
• Package durability and leakage characterized.
8JFET IC Wafer 10.1 vs past work1-2
• Aluminum Field Stop Implant to impede parasitic field MOSFETs.
• Heavily-implanted SiC contact regions were formed using phosphorus 
implant profile with slightly lower energy & dose.
• Contact was made using 50 nm sputtered titanium layer.
1D. J. Spry, et al., Mat. Sci. Forum 828 (2016) 908-912: “IC Wafer/Version 8.1”
2D. J. Spry, et al., IEEE Electron Device Lett. 37 (2016) 625-628: “IC Wafer/Version 9.2”
Primary design goal is extreme environment durability.
9Wafer 10.1 IC Functional Yield at 25 °C1
• JFET threshold voltage VT on depends on distance from the center of 
the wafer r, due to as-purchased wafer epilayer variation (see Ref. 2).
• Table I is for r < 25mm (on 38 mm radius wafer), the wafer region
where VT falls within circuit design specifications of |VT| < 10 V.
Despite > 7-fold increase in IC complexity from previous run (Wafer 9.2), 
functional probe yields in excess of 70% were obtained for Wafer 10.1.
1D. J. Spry, et al., presented at ICSCRM 2017, to appear in Materials Science
Forum, Vol. 924 (2018).
2P. G. Neudeck, D. J. Spry, and L. Chen, Proc. IMAPS High Temperature
Electronics Conf., 2016, pp. 263-271.
10
4X4 Random Access Memory (RAM) Demonstration Chip1
Address Decoder
Bit
4 X 4 RAM Cell Array
Bitline Read/Write Drive Circuitry
with Sense Amplifiers
Output Buffers
• 3mm x 3mm 4H-SiC 
JFET chip shown 
prior to packaging.
• 195 JFETs.
• 6-Transistor static 
RAM cell approach.
• Includes address 
decoders, read/ 
write bitline drive 
with sense 
amplifiers, output 
buffers. 
1D. Spry et al., ICSCRM 2017
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SiC JFET RAM Chip Circuit Design
RAM Cell
6-JFET cell mimics traditional “Static” RAM approach.
- Cross-coupled NOT gate latch connected to bit line pair by access FETs.
To enable “normally on” access JFETs function in “normally off” manner, 
latch is accessed at inverting amplifier stage and bit lines are internally 
driven/sensed using positive voltages.
204 µm
258 µm
National Aeronautics and Space Administration 12
Bit line (Column) Driver Schematic
SiC JFET RAM Chip Circuit Design
Internal chip word line (rows) and 
bit line (column) signals* at 500 °C
RAM Array Support Circuitry
*Waveforms measured via diagnostic bond pads 
and oven wiring to 10 MΩ oscilloscope probes.
• Address decoder and word lines function at negative voltages of logic family.
• Bit lines and sense amplifiers function at positive voltages (per preceding slide).
• Design is “proof of feasibility” for 500 °C operation, not considered “optimized”.
13
Measured 16-bit RAM waveforms showing read and write functionality
of all bits at 421 days (10,100 hours) of a 500 °C oven test.
RAM #2
VDD = +25 V
VSS = -25 V
VIL = -9 V
VIH = -1 V
14
Following modest changes during early burn-in period, output high (VOH)
and output low (VOL) voltage levels exhibit negligible change
RAM Chip Output Levels vs 500 °C Test Time
VDD = +25 V
VSS = -25 V
VIL = -9 V
VIH = -1 V
15
÷2/÷4 Clock Demonstration Chip1
21-Stage Ring Oscillator Clock
+ Output Buffers
Active
D Flip-Flops 2 or 
4
Select
LogicInactive
D Flip-Flop
High Frequency Ring Osc.
• 3mm x 3mm 4H-SiC 
JFET chip prior to 
packaging.
• 175 JFETs
• 21-Stage ring oscillator 
provides base 
frequency clock signal
• SELECT data line:
• High (0 V) à ÷4 output
• Low (-10 V) à ÷2 output
• Includes two D-type flip 
flops governed by select 
logic
• 3rd flip flop is inactive 
due to layout error.
• Optional modulation of 
high-f ring oscillator signal
1D. Spry et al., ICSCRM 2017
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Combination Logic Gate
SiC JFET Flip Flop Circuit Design
D-Type Flip Flop
• Ring oscillator base clock is frequency divided using D-
type flip-flops.
• Additional logic gates control signal propagation to realize 
2 vs 4 base clock frequency based on SELECT input.
17
Measured waveforms showing operation of ÷2/÷4 clock IC at
437.5 days (10,500 hours) of 500 °C oven testing.
÷2/÷4 Clock Chip #2
National Aeronautics and Space Administration 18
• Time evolution of ÷2/÷4 clock IC output voltages and frequency for all 5 
packaged chips subjected to prolonged 500 °C testing.
• After initial burn-in, output characteristics change < 10%.
• 3 of 5 chips remain functioning under 500 °C test today.
÷2/÷4 Clock Signals vs Time at 500 ° C
VDD = +25 V
VSS = -25 V
VIL = -10 V
VIH = -0 V
19
Wafer 10.1 500 °C Durability Results
First reported demonstrations of 1+ year (8766+ hours) 500 °C 
integrated circuit operation (in any semiconductor). 
National Aeronautics and Space Administration 20
Clock #1 IC Failure Analysis
White arrows denote examples of dielectric cracks and metal trace discoloration 
observed in the ring oscillator sub-circuit, symptoms of the primary 500 °C IC failure 
mechanism described previously1.
1D. J. Spry, et al., Proc. IMAPS High Temperature Electronics Conf., 2016, pp. 249-256. 
Electrical failure mode (at 470 hours): 21-stage ring oscillator ceased functioning.
National Aeronautics and Space Administration 21
Future Work
Continue development and demonstrations of 
increasingly capable 4H-SiC SiC JFET integrated 
circuits.
• Improve IC durability by reducing or eliminating 
dielectric crack formation.
• Improve IC capability by upscaling to higher chip 
complexity.
• Improve IC validation with larger statistical data 
sets, full flight environment electrical testing.
• Mature technology towards NASA mission insertion 
and commercialization.
National Aeronautics and Space Administration 22
Summary
Prototype IC designs meeting 4H-SiC JFET IC guidelines could potentially be 
fabricated by NASA Glenn, under negotiated collaborative Space Act Agreement: 
- Contact: https://technology.grc.nasa.gov, Priscilla.S.Diem@nasa.gov.
- Tech guidelines: https://sic.grc.nasa.gov/files/HiTEC2016-NeudeckV1A.pdf
First demonstration of 1+ year of 500 °C ambient 
temperature integrated circuit operation.
- 4H-SiC JFET ICs up to 195 transistors/circuit.
- First 500 °C durable random access memory (RAM). 
NASA Technology Access
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Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

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