This paper describes a comparison of two Montgomery
modular multiplication architectures: a systolic and a
multiplexed. Both implementations target FPGA devices. The
modular multiplication is employed in modular exponentiation
processes, which are the most important operations of some
public-key cryptographic algorithms, including the most popular
of them, the RSA. The proposed systolic architecture presents
a high-radix implementation with a one-dimensional array of
Processing Elements. The multiplexed implementation is a new
alternative and is composed of multiplier blocks in parallel
with the new simplified Processing Elements, and it provides a
pipelined operation mode. We compare the time × area efficiency
for both architectures as well as an RSA application. The systolic
implementation can run the 1024 bits RSA decryption process
in just 3.23 ms, and the multiplexed architecture executes the
same operation in 4.36 ms, but the second approach saves up to
28% of logical resources. These results are competitive with the
state-of-the-art performance