This paper focuses on super helical memory system's design, 'Engineering,
Architectural and Satellite Communications' as a theoretical approach of an
invention-model to 'store time-data'. The current release entails three
concepts: 1- an in-depth theoretical physics engineering of the chip including
its, 2- architectural concept based on VLSI methods, and 3- the time-data
versus data-time algorithm. The 'Parallel Time Varying & Data Super-helical
Access Memory' (PTVD-SHAM), possesses a waterfall effect in its architecture
dealing with the process of voltage output-switch into diverse logic and
quantum states described as 'Boolean logic & image-logic', respectively.
Quantum dot computational methods are explained by utilizing coiled carbon
nanotubes (CCNTs) and CNT field effect transistors (CNFETs) in the chip's
architecture. Quantum confinement, categorized quantum well substrate, and
B-field flux involvements are discussed in theory. Multi-access of coherent
sequences of 'qubit addressing' in any magnitude, gained as pre-defined, here
e.g., the 'big O notation' asymptotically confined into singularity while
possessing a magnitude of 'infinity' for the orientation of array displacement.
Gaussian curvature of k(k<0) is debated in aim of specifying the
2D electron gas characteristics, data storage system for defining short and
long time cycles for different CCNT diameters where space-time continuum is
folded by chance for the particle. Precise pre/post data timing for, e.g.,
seismic waves before earthquake mantle-reach event occurrence, including time
varying self-clocking devices in diverse geographic locations for radar systems
is illustrated in the Subsections of the paper. The theoretical fabrication
process, electromigration between chip's components is discussed as well.Comment: 50 pages, 10 figures (3 multi-figures), 2 tables. v.1: 1 postulate
entailing hypothetical ideas, design and model on future technological
advances of PTVD-SHAM. The results of the previous paper [arXiv:0707.1151v6],
are extended in order to prove some introductory conjectures in theoretical
engineering advanced to architectural analysi