International audienceAltitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65nm SRAMs

Autran, Jean-Luc

Gasiot, Gilles

Moindjie, Soilihi

Munteanu, Daniela

Roche, Philippe

English

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Multi-Poisson Process Analysis of Real-Time Soft-Error
Rate Measurements in Bulk 65nm SRAMs
Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Gilles Gasiot, Philippe
Roche
To cite this version:
Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Gilles Gasiot, Philippe Roche. Multi-Poisson
Process Analysis of Real-Time Soft-Error Rate Measurements in Bulk 65nm SRAMs. 28th European
Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2017), Sep 2017,
Bordeaux, France. ￿hal-01787603￿
  
   
 
 
 
 
Multi-Poisson Process Analysis of Real-Time Soft-Error Rate 
Measurements in Bulk 65nm SRAMs 
   
 S. Moindjiea,b, J.L. Autrana,b,*, D. Munteanua,b, G. Gasiotb,c, P. Rocheb,c 
   
 a Aix Marseille Univ, Univ Toulon, CNRS, IM2NP (UMR 7334), Marseille, France 
 b STMicroelectronics, Crolles, France 
 c Radiation Effects and Electrical Reliability (REER) Joint Laboratory, AMU-CNRS-ISEN-STMicroelectronics 
  
  
 
Abstract 
 
        Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed 
in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip 
multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the 
respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also 
offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, 
as illustrated here for bulk 65nm SRAMs. 
 
  
 
 
* Corresponding author.  
Jean-luc.autran@univ-amu.fr 
Tel: +33 (0) 413 594 627 
Multi-Poisson Process Analysis of Real-Time Soft-Error Rate 
Measurements in Bulk 65nm SRAM 
   
 S. Moindjiea,b, J.L. Autrana,b,*, D. Munteanua,b, G. Gasiotb,c, P. Rocheb,c 
   
  
 
 
  
1. Introduction 
 
Real-time soft error rate (RTSER) technique is an 
experimental reliability method to determine the soft 
error sensitivity of a given component, circuit or 
system [1]. The methodology consists in a direct 
observation of a large number of devices working in 
parallel under standard operating conditions and 
exposed to ambient background radiation at ground 
level. From the detection and counting of single events 
upsets occurring during the experiment, one can 
estimate the soft error rate (SER) of the devices under 
test. In case of SRAM circuits, the result can be given 
in terms of “event” SER, “total bit flip” SER, “multiple 
cell upset” (MCU) SER, and can be numerically 
expressed in FIT/Mbit (one FIT equals one failure per 
109 hours of operation) [2]. 
For modern CMOS circuits at terrestrial level, 
SER is the result of a weighting of two main 
components due to: i) the atmospheric particle flux and 
particularly the high-energy neutrons interacting with 
IC materials; ii) the traces of radioactive elements 
present in the circuit materials, mainly U or Th 
contaminations at sub-ppb concentrations. These two 
SER components are respectively labeled neutron-SER 
(n-SER) and alpha-SER (α-SER). Neutron-SER is 
proportional to the intensity of the high-energy neutron 
flux at test location whereas alpha-SER is fixed and 
linked to the concentrations of radioactive impurities. 
The measured SER at a given test location is generally 
expressed as [2,3]: 
 SERtest  location = AF × n-SERNYC +α-SER  (1)  (  ( 
where AF is the so-called acceleration factor [3] which 
define the relative neutron flux at test location with 
respect to sea-level (reference New York City, NYC) 
and  n-SERNYC is the value of the neutron-SER 
normalized for NYC conditions. From Eq. (1), it is 
obvious that α-SER can be directly measured during 
an underground experiment (AF = 0) and that 
measurements at two different locations is sufficient 
for determining the two unknown quantities n-SERNYC 
and α-SER.   
  
 In this study, altitude (on the ASTEP platform [2]) 
and underground (at LSM, Modane [4]) real-time soft 
error rate (SER) measurements on bulk 65nm SRAM 
circuits have been analyzed in terms of independent 
multi-Poisson processes describing the occurrence of 
single events as a function of bit flip multiplicity. This 
approach has been applied for estimating the event 
rates induced by atmospheric neutrons and alpha-
particle emitters as a function of event multiplicity. We 
used these extracted results to predict by simulation the 
radiation response of the 65nm SRAMs for a third test 
location at sea-level (Marseille, France), illustrating the 
advantage of this method not only to evaluate the 
global SER value but also to accurately estimate the 
occurrence of MCU events as a function of their event 
multiplicity. q .  
 
2. Theory 
 
 The occurrence of soft errors in electronics is a 
continuous time stochastic process. The principle of a 
RTSER experiment is to count the number of random 
events N(t) that have occurred up to some point t in 
time over a large population of circuits (the number of 
events is therefore small relative to the number of 
memory elements considered in the test). In such a 
real-time approach, soft errors are not permanent 
because they are eliminated when new data is written 
after detection: a RTSER test is thus equivalent to a 
life-test with replacement, i.e. in which a failing device 
is replaced with a new device immediately upon failure 
detection. Assuming that soft errors are also random in 
space (within the circuits), independent of each other 
and occur with a fixed event rate λ, the counting 
process {N(t), t ≥ 0} in a finite interval of time t 
consequently obeys the Poisson(λt) distribution [4]: 
 P(N(t) = n) = e
−λt (λt)n
n! , n = 0, 1, 2 (2)  (  (1) 
 The maximum likelihood estimate for λ is simply 
the number of detected events N divided by the 
experiment duration T and eventually normalized with 
respect to the number of units on test. Expressing this 
later quantity in Mbit for a memory test and time in 
MBit×h, λ can be directly estimated from: 
  λ = N/ Σ (3) 
where Σ is the number of MBit×h cumulated at time T 
given by: 
 Σ = MEM (t)dt
0
T
∫  (4) 
where MEM(t) represents the number of Mbit under 
test at time t. This quantity may be variable in case of 
device automatic disconnection by the system due to 
abnormal current consumption or other anomaly 
detected at device, daugthercard or mothercard levels.  
 
 The counting process, previously introduced, can 
be applied to “single events” (whatever the type of 
these events), or more specifically to single bit upsets 
(SBU) or to multiple cell upsets (MCU) defined by a 
given event multiplicity (noted MCU(q), q = 2, 3,.. 
corresponding to the number of bitcells simultaneously 
upset during a same particle interaction event). Let 
N1(t), N2(t),…. Ni(t), … NM(t) be M independent 
Poisson processes with event rates λ1, λ2,…, λi,… λM 
respectively corresponding to the counting of SBU, 
MCU(2), …, MCU(i),… MCU(M) events. The total 
event counting process N(t) = Σ Ni(t) will be the 
merging of all these Poisson processes and will be also 
a Poisson process with rate  λ = λ1 + λ2 +…+λi… + 
λM, as illustrated in Fig. 1. 
 
Process 1, N1(t), SBU 
 
Process 2, N2(t), MCU(2) 
 
Process 3, N3(t), MCU(3) 
. 
. 
. 
Process M, NM(t), MCU(M) 
 
Merged process, N(t) 
 
t!
t!
t!
t!
t!
 
Figure 1. Merging M Poisson processes corresponding to the 
occurrence of single events of different cell upset 
multiplicities. 
 
 Performing such a multi-Poisson process 
decomposition of the global “single event” process 
occurring during a RTSER experiment will allow us to 
reveal the respective contributions of atmospheric 
neutrons and alpha-particle emitters in the MCU SER 
response of the technology under test, as illustrated in 
the following. 
 
3. Real-time experiments 
 
 For the purpose of this study, we considered raw 
data of three RTSER experiments performed on 3,226 
Mbit of bulk 65nm Single-Port SRAMS (using two 
identical test setups) between 2008 and 2017. Details 
about these experiments can be found in Refs. [2, 5-7]. 
Table I summarizes these experiments conducted on 
the ASTEP platform (2,255 m of altitude) in 2008-09, 
at the underground laboratory of Modane (LSM) 
between 2008 and 2015 and at sea-level in Marseille 
(IM2NP laboratory) since 2014. This last experiment is 
always running in 2017. 
 
Table 1. Summary of the 65nm SRAM RTSER experiments. 
Location 
Acceler. 
factor 
AF 
Start date 
Stop date 
Effective 
cumulated 
hours of tests 
ASTEP 6.5 01/21/2008 05/07/2009 11,278 
LSM 0 04/11/2008 01/25/2015 57,058 
Marseille 0.9 10/16/2014 Ongoing* 17,233 
*Results reported on 02/28/2017 
 
 Figures 2 to 4 show the cumulative bit flips 
distributions versus test duration obtained for the three 
experiments. Test has been conducted under nominal 
operating conditions: VDD = 1.2V, room temperature, 
standard checkerboard test pattern. These results will 
serve as raw data for the multi-Poisson process 
analysis conducted in the next section. 
 
 0
 20
 40
 60
 80
 100
 0  2000  4000  6000  8000  10000  12000
65 nm Single-Port SRAM - ASTEP
Cu
mu
la
te
d 
nu
mb
er
 o
f 
bi
t 
fl
ip
s
Time (hours)  
Figure 2. Cumulated distribution of bit flips versus time for 
the altitude experiment on the ASTEP platform. 
 0
 50
 100
 150
 200
 0  10000  20000  30000  40000  50000  60000
65 nm Single-Port SRAM - LSM
Cu
mu
la
te
d 
nu
mb
er
 o
f 
bi
t 
fl
ip
s
Time (hours)  
Figure 3. Cumulated distribution of bit flips versus time for 
the underground experiment at LSM. 
 
 0
 10
 20
 30
 40
 50
 60
 70
 80
 0  4000  8000  12000  16000
65 nm Single-Port SRAM - Marseille
Cu
mu
la
te
d 
nu
mb
er
 o
f 
bi
t 
fl
ip
s
Time (hours)  
Figure 4. Cumulated distribution of bit flips versus time for 
the sea-level experiment in Marseille. 
 
4. Results and discussion 
 
 From raw data on Figs. 2 to 4 and because the 
three experiments involved the same quantity of 
memory (3,226 Mbit), we first extracted in Tables 2 to 
4 the event rate per hour (number of events divided by 
the experiment duration) of single events as a function 
of the event multiplicity (an event of unit multiplicity 
corresponding to a single bit upset). 
 
Table 2. Event rate extraction from RTSER data for the 
altitude experiment on ASTEP platform. 
Event 
multiplicity 
Number of 
Events 
Event rate 
(h-1) 
1 44 λ1 = 3.90×10-3 
2 7 λ2 = 6.21×10-4 
3 5 λ3 = 4.43×10-4 
4 3 λ4 = 2.66×10-4 
5 1 λ5 = 8.87×10-5 
6 1 λ6 = 8.87×10-5 
7 1 λ7 = 8.87×10-5 
 
Table 3. Event rate extraction from RTSER data for the 
underground experiment at LSM. 
Event 
multiplicity 
Number of 
Events 
Event rate 
(h-1) 
1 109 λ1 = 1.91×10-3 
2 24 λ2 = 4.21×10-4 
3 12 λ3 = 2.10×10-4 
4 2 λ4 = 3.51×10-4 
5 2 λ5 = 3.51×10-5 
6 2 λ6 = 3.51×10-5 
7 0 λ7 = 0 
 
Table 4. Event rate extraction from RTSER data for the sea-
level experiment at Marseille. 
Event 
multiplicity 
Number of 
Events 
Event rate 
(h-1) 
1 36 λ1 = 2.09×10-3 
2 9 λ2 = 5.22×10-4 
3 4 λ3 = 2.32×10-4 
4 0 λ4 = 0 
5 1 λ5 = 5.80×10-5 
6 0 λ6 = 0 
7 0 λ7 = 0 
 
 From Eq. (1) also valid in terms of event rate, one 
can consider that for a given test location: 
 λi = AF × n-λi +α-λi  (5)  (  ( 
where λi, n-λi and α-λi are respectively the total, 
neutron and alpha event rates for events of multiplicity 
i (i=1, 2,…). 
 
 Considering Eq. (5) for both ASTEP (AF = 6.5) 
and LSM (AF = 0) experiments, it is then possible to 
extract these n-λi and α-λI values for the 3,226 Mbit of 
tested devices. This extraction is reported in Table 5 
and illustrated in Fig. 4. These results show that, for 
this particular bulk 65nm technology, soft errors are 
dominated by the contribution of alpha-particle 
radioactivity present in IC materials up to events of 
multiplicity equal to 6. In particular, the alpha event 
rate is 6 times larger than neutron event for SBU, 7 
times larger for MCU(2), 5 times larger for MCU(3) 
and 4 times larger for MCU(5) and MCU(6). Neutrons 
and alphas have finally similar event rate for MCU(4) 
whereas neutrons seems to dominate for larger MCUs.  
  
  
 In order to verify the validity of such extractions, 
we use on more time Eq. (5) to estimate the alpha and 
neutron event rates for Marseille location from data of 
Table 5 extracted by the combination of ASTEP and 
LSM results. Taking AF = 0.9 for Marseille, Table 6 
shows the results of the so-called “predicted” event 
rates using this procedure. These values are compared 
to the experimental (i.e. measured) event rates and are 
used to “predict” the number of events vs. multiplicity 
for a fixed duration of 17,233 h corresponding to the 
measurements. Table 5 shows that these predicted 
values are very close to the measured ones, 
demonstrating here the interest of such a multi-Poisson 
process analysis to calculate not only the global event 
rate of the circuits but also to quantify the respective 
contributions of MCU events as a function of event 
multiplicity. In the conference presentation and in the 
final paper, a similar analysis will be applied to bulk 
40nm SRAMs for which results extracted from altitude 
and sea-level experiments [8] will show more 
contrasted results between neutron and alpha 
contributions to MCU events with multiplicities 
ranging up to 22. 
 
References 
 
[1] J.L. Autran and D. Munteanu, Soft Errors: from particles 
to circuits, Taylor & Francis/CRC Press, 439 p., 2015. 
[2] J.L. Autran, D. Munteanu, G. Gasiot, P. Roche, 
Microelectronics Reliability, vol. 54, pp. 1455-1476, 
2014. 
[3] JEDEC Standard "Measurement and Reporting of Alpha 
Particles and Terrestrial Cosmic Ray-Induced Soft Errors 
in Semiconductor Devices", JESD89 Arlington, VA: 
JEDEC Solid State Technology Association, 2006. 
[4] J.F.C. Kingman, Poisson Processes, Clarendon Press, 112 
p., 1992. 
[5] J.L. Autran, D. Munteanu, S. Moindjie, T. Saad Saoud, S. 
Sauze, G. Gasiot, P. Roche, Microelectronics Reliability, 
Vol. 55, pp. 1506-1511, 2015. 
[6] J.L. Autran, D. Munteanu, S. Sauze, G. Gasiot, P. Roche, 
2014 IEEE Radiation Effects Data Workshop (REDW), 
pp.1-8, 14-18 July 2014. 
[7] J.L. Autran, P. Roche, S. Sauze, G. Gasiot, D. Munteanu, 
P. Loaiza, M. Zampaolo, and J. Borel, IEEE Transactions 
on Nuclear Science, vol. 56, no. 4, pp. 2258-2266, Aug. 
2009. 
[8] J.L. Autran, S. Serre, D. Munteanu, S. Martinie, S. 
Semikh, S. Sauze, S. Uznanski, G. Gasiot, L. Dugouyon, 
P. Roche, International Reliability Physics Symposium 
(IRPS’2012), Anaheim, USA, April 15-19, 2012, 3C-5.  
 
 
Table 5. Extracted values of neutron and alpha event rates 
from data of Tables 2 and 3 using Eq. (5). 
Event 
multiplicity 
Neutron event 
rate (h-1) 
Alpha event 
rate (h-1) 
1 n-λ1 = 3.06×10-4 α-λ1 = 1.91×10-3 
2 n-λ2 = 3.08×10-5 α-λ2 = 3.33×10-4 
3 n-λ3 = 3.59×10-5 α-λ3 = 2.10×10-4 
4 n-λ4 = 3.55×10-5 α-λ4 = 3.51×10-5 
5 n-λ5 = 8.25×10-6 α-λ5 = 3.51×10-5 
6 n-λ6 = 8.25×10-6 α-λ6 = 3.51×10-5 
7 n-λ7 = 1.36×10-5 α-λ7 = 0 
 
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0.0010$
0.0100$
0.1000$
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at
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&(p
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Figure 4. Neutron and alpha event rates as a function of event 
multiplicity as extracted in Table 5. 
 
Table 6. Event rate extraction from RTSER data for the sea-
level experiment at Marseille. 
Event 
multi- 
plicity 
Number of Events Event rate (h-1) 
Measured Predicted Measured Predicted 
1 36 38 2.09×10-3 2.18×10-3 
2 9 6 5.22×10-4 3.72×10-4 
3 4 4 2.32×10-4 2.42×10-4 
4 0 1 0 6.67×10-5 
5 1 1 5.80×10-5 4.24×10-5 
6 0 1 0 4.24×10-5 
7 0 0 0 1.21×10-5 
TOTAL 50 51 
 


Multi-Poisson Process Analysis of Real-Time Soft-Error Rate Measurements in Bulk 65nm SRAMs

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Multi-Poisson Process Analysis of Real-Time Soft-Error Rate Measurements in Bulk 65nm SRAMs

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