Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the
delay of any path can be calculated. Moreover, a comparison
of the fine-grained delays allows a detailed understanding of
the amount and type of process variation that exists in the
FPGA. To obtain these delays, Timing Extraction measures,
using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We
apply Timing Extraction to the Logic Array Block (LAB)
on an Altera Cyclone III FPGA to obtain a view of the
delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred
picoseconds with a resolution of ±3.2 ps. This information
reveals that the 65 nm process used has, on average, random
variation of σ/µ = 4.0% with components having an average maximum spread of 83 ps. Timing Extraction also shows
that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV
60 nm FPGA, paths slow down and variation increases from
σ/µ = 4.3% to σ/µ 5.8%, a clear indication that lowering
V_(DD) magnifies the impact of random variation
