A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics

Abstract

A physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2-D potential profile information. Each is verified via numerical calculations and 2-D electrostatic simulation, followed by a comparison of the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations.Manuscript received April 29, 2009; revised September 9, 2009. First published October 30, 2009; current version published November 20, 2009. This work was supported in part by NSF under Grant ECS 0501096, by the Focus Center Research Program (MSD), and by Intel Corporation. The work of S. Oh was supported in part by the Samsung Scholarship and in part by The Burt and Deedee McMurtry Stanford Graduate Fellowship Fund. The review of this paper was arranged by Editor M. Anwar