Copyright © 2004 IEEEParallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi and Michael J. Liebel

Al-Sarawi, S.

Celenski, P.

Liebelt, M.

Townsend, T.

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Hybrid parallel counters - domino and threshold logic

Adelaide Research &amp; Scholarship

Hybrid Parallel Counters – Domino and Threshold LogicTroy D. Townsend, Peter Celinski, Said F. Al-Sarawi and Michael J. LiebeltThe School of Electrical and Electronic Engineering,The University of Adelaide, SA 5005, AustraliaE-mail: {troy,celinski,alsarawi,mike}@eleceng.adelaide.edu.auAbstractParallel counters are the building blocks of partial prod-uct reduction tree (PPRT) circuits, which are required forhigh-performance multiplication. In this paper we willimplement novel counters using a hybrid of domino andthreshold logic. A test 64 × 64 PPRT using these coun-ters was found to reduce latency by 39% and device countby 38% compared to the domino logic equivalent.1 IntroductionThe partial product reduction tree (PPRT) is the most de-lay and area intensive portion of a high performance parallelmultiplier [3, 5, 6] and is the focus of this paper. The PPRTis typically constructed using small parallel counters [5] asCMOS is most efﬁcient at low fan-in.The primary performance objective for our designs is la-tency – throughput can be set by varying the pipeline depthand degree of parallelism; latency reductions save area andpower by removing pipeline latches.We will measure time delays using logical effort anal-ysis [7]. Accurately estimating power consumption andwiring overhead are beyond the scope of this paper, so wewill use device count to gauge efﬁciency.To implement threshold logic, we will use Charge-Recycling Threshold Logic (CRTL) [2]. Each gate com-putes a threshold function, which is speciﬁed by the gatethreshold T and the weights w1, w2, . . . , wn; wi is theweight associated with the i th input variable xi. The outputy is high when∑ni=1 wixi ≥ T and low otherwise.All domino logic in this paper is dual rail, sized to pro-vide an input loading equivalent to a minimum-sized in-verter, with such an inverter buffering each gate’s output.We have obtained logical effort parameters for domino logicfrom simulations; the parameters for CRTL are providedby [1]. As both CRTL and domino are typically operatedon a 50% duty cycle, we can compare them solely on thebasis of evaluation delay.2dbascFigure 1. Hybrid 3:2 counter circuit2 Counter implementationsA standard 3:2 counter (“full adder”) circuit [5, 6] andassociated model appear to be prevalent; we will implementit using domino logic. This model ﬁnds the sum output to becomputed at time s = max (b + x2, d + x3) and the carryoutput at c = d + y3, for input delays a ≤ b ≤ d and pathdelays x2, x3 and y3.The Minnick family of counters [4] are the fastest knownTL implementation. We can construct a hybrid 3:2 counterby using this to compute the carry output and domino tocompute the sum output, as seen in Figure 1.Some threshold logic families (including CRTL) cansupport high fan-in much more effectively than CMOS, per-mitting efﬁcient larger counters. However, CRTL gates canonly resolve a limited set of voltage steps, which mandatesthat we limit fan-in (sum of input weights) to 30 for eachCRTL gate [1] – enough for 7:3 and 15:4 counters. We willimplement larger hybrid counters by using domino logic (atree of XOR gates) to implement the least signiﬁcant outputand the Minnick architecture for the others. This is exem-pliﬁed by Figure 2, which shows a 15:4 hybrid counter.3 ComparisonIn order to optimise signal delays, all counter outputsare synchronised to multiples of a time quantum, which wewill name φ – in this fashion we can take into account fasterand slower paths through a counter rather than assumingall are equal, providing better optimised circuits. For thestandard 3:2 counter φ is taken to be the larger of the XORand majority functions’ computation times [5].Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-2097-9/04 $20.00 © 2004 IEEE                            O 1OO O48 2−8V15481224−4−4−4Figure 2. Hybrid 15:4 counter circuitTable 1. 3:2 counter comparisonCircuit A L φ x2 x3 y3(κ) (τ ) (τ ) (τ ) (τ )Domino 66 3 6.42 12.8 6.4 12.8Minnick 36 2 4.33 8.6 8.6 4.3Hybrid 41 2 5.42 10.8 5.4 5.4Table 1 shows area, loading and performance (latencyand throughput) information for each of the 3:2 counters.Area A is measured in terms of device (transistor or capac-itor) count; input load L is measured in terms of κ, the loadpresented by a minimum-sized inverter. The unit of time isτ , the delay of a parasitic-free minimum-sized inverter driv-ing a load of κ (commonly used in logical effort analysis).It is clear from the table that both Minnick and hybrid coun-ters outperform the domino circuit, despite placing a lowerload on the input and requiring signiﬁcantly less area.To compare counters for use in heterogeneous circuits,we will restrict each circuit to φ = 6.42τ and L ≤ 3κ,matching the parameters of the domino 3:2 counter. Ta-ble 2 provides latency and area data for a number of differ-ent counters under these conditions. Area (device count) isnormalised against the domino 3:2 counter – that is, for acounter reducing i bits (e.g. the 15:4 counters reduce 11bits), normalised area An = Ai.Ar , where Ar is the devicecount of the domino 3:2 counter. For simplicity, the tabledoes not consider “fast inputs” – each of the hybrid countersare slightly faster than listed under some circumstances.We note that each hybrid is faster than its Minnick equiv-alent and also that the 7:3 and 15:4 versions require lessarea. Thus heterogeneous circuits should be constructedsolely using hybrid counters in order to achieve lowest la-tency.An initial comparison of PPRT performance using thesecounters was undertaken at 64 × 64. The three-greedy al-gorithm [5] was used for the homogeneous circuits as thecomputation requirements for ﬁnding optimal circuits [6]were too great; heterogeneous circuits were constructed us-Table 2. Counter comparison with ﬁxed φ, LCircuit O8 O4 O2 O1 An(φ) (φ) (φ) (φ)Minnick 3:2 1 2 55%Hybrid 3:2 1 2 62%Minnick 7:3 2 3 3 54%Hybrid 7:3 1 2 3 45%Minnick 15:4 3 4 4 4 78%Hybrid 15:4 2 3 3 4 54%ing the algorithm in [8]. Final latency was found to be 18φfor domino, 15φ for both Minnick 3:2 and hybrid 3:2 ho-mogeneous circuits, and 11φ for the heterogeneous circuit.The area of the homogeneous circuits is proportional to An(refer to Table 2); the heterogeneous circuit will reduce de-vice count by at least 38% compared to domino.4 ConclusionA 64× 64 PPRT circuit implemented with hybrid coun-ters of varying sizes was found to reduce latency by 39%and device count (area) by at least 38% compared to thoseof domino logic. This is an encouraging result, and futureoptimisation is expected to improve this even further.References[1] P. Celinski, S. D. Cotofana, and D. Abbott. A logical effortbased delay model of charge recycling threshold logic gates.In Proc. ProRISC Workshop on Circuits, Systems and SignalProcessing, Veldhoven, Netherlands, November 2003.[2] P. Celinski, J. F. Lo´pez, S. Al-Sarawi, and D. Abbott. Lowpower, high speed, charge recycling CMOS threshold logicgate. IEE Electronics Letters, 37(17):1067–1069, August2001.[3] L. Dadda. On parallel digital multipliers. In E. E. Swartzlan-der, Jr., editor, Computer Arithmetic, volume I, pages 126–132. IEEE Computer Society Press, 2nd edition, 1990.[4] R. C. Minnick. Linear-Input Logic. IRE Transactions onElectronic Computers, EC-10:6–16, March 1961.[5] V. G. Oklobdzija, D. Villeger, and S. S. Liu. A method forspeed optimized partial product reduction and generation offast parallel multipliers using an algorithmic approach. IEEETransactions on Computers, 45(3):294–306, March 1996.[6] P. F. Stelling, C. U. Martel, V. G. Oklobdzija, and R. Ravi.Optimal circuits for parallel multipliers. IEEE Transactionson Computers, 47(3):273–285, 1998.[7] I. E. Sutherland, R. F. Sproull, and D. L. Harris. LogicalEffort: Designing Fast CMOS Circuits. Morgan Kaufmann,1999.[8] T. D. Townsend, P. Celinski, S. F. Al-Sarawi, and M. J.Liebelt. A hybrid approach for multiplier design. To be sub-mitted to Great Lakes Symposium on VLSI, Boston, USA,April 2004.Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-2097-9/04 $20.00 © 2004 IEEE

Hybrid parallel counters - Domino and threshold logic

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Hybrid parallel counters - Domino and threshold logic

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Hybrid parallel counters - Domino and threshold logic

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Adelaide Research &amp; Scholarship

Adelaide Research & Scholarship