This paper presents a scheduler for Data-Flow threads implemented in reconfigurable logic for being
deployed on Reconfigurable MPSoCs (i.e., Multi-Processing System on Chips with FPGA). "Data-Flow
threads" (DF-Threads) is a novel execution model for mapping threads on local or distributed cores
transparently to the programmer. This model is capable of being parallelized massively among different
cores and it handles even hundreds of thousands or more Data-Flow threads, and their associated data
frames, in order to distribute them both in a local node and through the network to other nodes in a
transparent way. The Hardware Scheduler (HS) is designed for being used in Programmable Logic (PL) of
MPSoC FPGAs and it deals with the GPP cores, providing them with Data-Flow threads ready to be
executed. The overall design is modeled and tested through the HPLabs COTson simulator. Here we use
the Block Matrix Multiply benchmark to analyze the potentiality of the proposed model