Amplificador de potencia clase F a 1.64 ghz con control de armónicos

Abstract

This paper presents a high-power high efficiency PA design method using load pull technique. Harmonic impedance control at the virtual drain is accomplished through the use of tunable pre-matching circuits and modeling of package parasitics. A 0.5 µm GaN high electron mobility transistor (HEMT) is characterized using the method, and loadpull measurements are simulated illustrating the impact of varying 2nd and 3rd harmonic termination. These harmonic terminations are added to satisfy conditions for class-F load pull. The method is verified by design and simulation of a 40-W class-F PA prototype at 1.64 GHz with 76% drain efficiency and 10 dB gain (70% PAE)