ConferenciaA simple approach for the design, fabrication and
characterization of a operational trasconductance amplifier intended
for work in low power applications is reported in this
work. DC Measured parameters agree with simulation results
and specifications. An application for the designed OTA is also
tested.


Chacón-Rodríguez, Alfonso

Julián, Pedro

Mandolesi, Pablo

Sondon, Santiago

English

Repositorio Institucional del Instituto Tecnologico de Costa Rica

A Simple Approach for the Design of Operational Transconductance Amplifiers for Low Power Signal Processing Alfonso Chacon-Rodriguez Escuela de Ingenieria Electronica Instituto Tecnologico de Costa Rica Santiago Sondon Pablo Mandolesit Pedro Julian* Apartado Postal: 159-7050, Cartago 30101, Costa Rica Email: a1chacon@itcr.ac.cr GISEE Universidad Nacional del Sur Abstracl-A simple approach for the design, fabrication and characterization of a operational trasconductance amplifier in­tended for work in low power applications is reported in this work. DC Measured parameters agree with simulation results and specifications. An application for the designed OTA is also tested. I. INTRODUCTION As it has been reported extensively on literature, linearized transconductors find wide application in low power signal processing. In this case, a continuous Gm-C paralell filter bank, and several analog computing structures were to be build on a CMOS 0.5 /Lm process, in order to implement a contin­uous gunshot detector [1]. The signals to be processed have a required bandwidth of [100Hz, 1250Hz], and a maximum peak voltage swing of 550m V. The detector is intended for its use in surveillance wireless sensor network against illegal hunting in tropical forest reserve. As such, power consumption is critical and each component must be adequately sized. Usually, most of the available equations and relationships used for the design of transconductors are based on the long channel quadratic equations [2], [3], though there are some approximations in the literature to the design of OTAs using the weak inversion models of the transistor [4]. And while there is also plenty of literature on the design of OTAs and operational amplifiers [5]-[8], as well as other complex structures [9], [10], using the EKV or the ACM MOSFET models, there is nonetheless scarce material on a similar design approach for standard linearized transconductors. We propose in this paper a simple approach for the design of the ubiquitous Krummenacher's linearized CMOS OTA [11], with equations derived from the EKV model, and show an example of its implementation. The paper is organized 'P. Julian is member of Consejo Nacional de Investigaciones Cientificas y Tecnicas CONICET, Av. Rivadavia 1517, Buenos Aires, Argentina. tP. Mandolesi is member of CIC (Comision de Investigaciones Cientificas), Pcia. Bs. As, La Plata, Argentina. Alem 1253, Bahia Blanca, Argentina Email: {ssondon.pmandolesi}@uns.edu.ar pjulian@ieee.org as follows: Section II presents the general process used for the design of an OTA intended for low power applications. Section III presents a case study of a particular design and its simulation results. Section IV presents measurements of the case study. Finally, Section V concludes the paper and discuss the oncoming work. II. DESIGN PROCESS OF AN OPERATIONAL TRANSCONDUCTANCE AMPLIFIER A typical linearized OTA, as proposed by Krummenacher in [11] and shown in Fig. 1, has an optimum size relation of 6.7 between the sizes of the difussor and the input differential transistor pairs. This relation is derived directly from the long channel MOS quadratic equations. In [4], an alternative relation of 2 is derived, when the transistors are to be operated in the weak inversion region. In the first case, the total OTA Gm equals approximately 4.7 times the input transistor's gm, while in the second case, this relation is of approximately 3. In our case, the OTA's slew rate and power requirements implied transistors working near the moderate inversion region, but with a linearized Gm characteristic with an input range of at least 1 Vpp. To avoid a tiresome simulation approximation, an analytic expression for the equivalent transconductance was derived from the EKV model [12]. From these equations, using Krummenacher's optimum transistor relation, an expected OTA Gm can be obtained in terms of the transistors' gm, if the transistors are taken from the moderate inversion region towards the strong inversion zone. If K is the OTA's transconductance in terms of the input transistors' gm, then (1) Analitically, Gm can be expressed as (see [13]): (2) 978-1-5090-2076-8/10/$31.00 ©201 0 IEEE 160 Fig. 1. PMOS Krummenacher's OTA. PMOS input transistor are chosen due to their intrinsic lower transconductance. If one considers that (3) with GiJx the normalized transconductance x in terms of the maximum transconductance, Eq. (2) may be re-written as G � gmMl m  G 2+� 2GiJ2 (4) If transistor M2 is scaled in terms of MI, and assuming both biased with the same current, then M2 may end up in a different inversion region than MI. Following the EKV basic equations [12], one may define inversion currents ifl e if2 for each transistor. Since (5) with (6) the specific current for the process, and using the aspect relation between the transistors, then VI + 0.5y7 vT'n + 7ifl VI + 0.5vT'n + ifl (7) Solving this equation, one can then find out the wanted transconductance relation (8) Intuitively, one can verify that, for i fl « 1, K � 3, whereas if i fI » 1, K � 4.64. Both values verify Eq. (2) when the transistors are in the weak inversion region (where gmMl � gmM2 � IBIAs/ncp), and the well known relation when they are in the strong region zone (see [13]). Figs. 2 y 3 show the variation of K = Gm/ gm in terms of the normalized transistor transconductance G( if) and its inversion level if, as defined by the EKV model. 161 III. CASE STUDY The goal was to design a paralell filter with three specific pass-bands: [875Hz,437Hz], [437Hz,219Hz] and [219Hz,109Hz]. Since 875Hz was the top 3dB cutoff fre­quency, and the chosen sizes of the capacitors where in the order of 25pF to 50pF, a slew rate of 2.75 mV/J..Ls was specified as the starting point for the design. This particular slew rate implied a minimum bias current of almost 70nA, that was taken to 90nA to account for possible extra parasitic capacitances or peak signals a little above the expected 500m V. Simulations with arbitrary transistor sizing but following Krummenacher's 6.7 size ratio showed that placing the tran­sistors from the moderate too much towards the weak inversion zone ruined the linearization, as the diffusors were taken from the triode into the saturation region when the input differential voltage approached zero. Using a smaller transistor ratio solved the issue, at the cost of a smaller linear zone, as already shown in [4]. The compromise was found by choosing always moderate inversion, but slightly into the strong inversion zone, with a if of 3 to 4 and a final normalized transconductance between a 40% to 35% of the maximum one (GiJ � 0.4 * ID/nVT) [12]. Gm versus gml = f(Gi 4.8,-----,-----,---,----.-- ,---.::.c.c..:,::---=-,.:........:-'-'r----,---, 4.6 4.4 4.2 3.8 o .� 0:: 3.6 3.4 3.2 30L-�,0,---2�O-�3�O -�40,---=50-�6�O-�70�-=80-�9�Q -�100 Nonnalized transconductance GiJ (l/nUt) Fig. 2. Ratio between the OTA transconductances and the input transistors' K = gmMI!Gm, as a function of the normalized transistors' transconduc­tance f(GiJ). A basic 137nS OTA was designed to provide for the top cutoff frequency. The rest of the cutoff frequencies were to be obtained by scaling this transconductor using the current division technique proposed in [5], and by adding or sub­stracting the corresponding capacitor sizes. A Matlab script containing the derived equations was used for the sizing of the transistors in terms of the expected transconductance, using as input parameters the bias current and the intended inversion level. If the transistor length parameter was used as an input as well, the script provided then with information about the parasitic capacitances resulting from the calculated transistor sizes. Results were then checked against an Eldo 4.6 4.4 4.2 3.8 o .� 0:: 3.6 3.4 3.2 10° 101 Inversion level if Fig. 3. Ratio between the OTA transconductances and the input transistors' K = gmMI!Gm, as a function of Ml inversion level if. spice simulation, approximating the required sizes by a series­parallel association of unitary transistors. These unitary tran­sistors were all long channel ones chosen with sizes as close as possible to those used by the foundry to generate their BSIM models. Simulations also allowed for a confirmation of the expected linear range. As a whole, it took no more than a few iterations to obtain the definitive transistor sizes. Transconductance simulation results are shown in Fig. 4. C2:0.47000(dx_943.3HHM) Fig. 4. Simulation of OTA's output current and transconductance. The layout technique used was proposed in [5], [14]. Here, input and diffusor transistors are piled up and intermixed, to improve matching. An example for a 34nS OTA is shown in Fig. 5, where the final transconductance is obtained by dividing the input's 137nS by a factor of four, using the aforementioned current division technique. An IC with the intended paralell filter bank was designed using the Mentor Graphics environment, but leaving aside a single 137nS OTA structure for its separate characterization. 450 900 1350 1800 450 900 1350 1800 Fig. 5. Layout example. In this case, a 34.25nS OTA, based on a 137nS input OTA, with its transconductance scaled down by current division [5]. Input and diffusor transistors, as well as the division mirror ones are piled up and intermixed using the technique proposed in [5], [14] IV. MEASUREMENTS For DC signal injection and measurement an Agilent E5270B framework with E5287 A modules was used. Instru­ments were operated remotely through a GPIB bus with a computer runing a script in MatLAB. The tested OTA had a regulated input bias, to adjust its transconductance. VDD was 4V. In Fig. 6 and Fig. 7 measured transference curve and calculated transconductance are shown respectively. 1X 10-7 0.8 0.6 0.4 $0.2 0: 0 � :::>-0.2 U �.4 Q. 5-<1.6 0 -<l8 -'0 0.5 1.5 2 2.5 3.5 V+ Voltage (V) Fig. 6. Measured transference curve for OTA. 0.5 1.5 2 2.5 V+ Voltage (V) Fig. 7. Calculated transconductance curve for OTA. Parameters extracted from measurements are shown on table I. Measurements evidence that for the intended 90nA input 162 current bias, the obtained transconductance has an error of 5% from the expected one. OTA's frequency response shows that gain and bandwith are well for the intended application. TABLE I MEASURED OTA's DC PARAMETERS 11 12 V- Transconductance Offset Linear range 30 nA 30 nA 2V 104 nS 4.6 mV 970 mV 45 nA 45 nA 2V 130 nS 6.3 mV 1000 mV 45 nA 45 nA 1.75 V 132 nS 6.3 mV 1000 mV 45 nA 45 nA 2.25 V 132 nS 2.3 mV 1100 mV 60 nA 60 nA 2 V 152 nS 5.1 mV 1000 mV 40 nA 50 nA 2 V 129.6 nS - 45.7 mV 1000 mV The AC response of the intended bank of filters, as im­plemented on two different IC's is shown in Fig. 8. The adjustable bias current of the OTAs allowed for a fine tuning of the cutoff frequencies, to compensate for capacitance and transconductance process deviations. Some extra adjustment was required due to the high input capacitance of some of the OTAs, that also produced a sharper roll off on the first bank. This deviation was nonetheless an effect of the chosen filter topology, and may be easily corrected. In general the design process of the OTAs showed to be fast and relatively precise. V. CONCLUSIONS A simple method for the quick design of linearized OTAs working in the moderate inversion regime has been shown. The method has been tested with the implementation of various transconductors that have been used later as components of a Gm-C bank filter. Testing results of a particular OTA were within 5% of the expected transconductance, with a linear range of 1 V pp and a bias current of only 90nA. REFERENCES [I] A. Chacon-Rodriguez and P. Julian, "Evaluation of gunshot detection algorithms," 2008, pp. 49-54. [2] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. McGraw-Hili Science/Engineering/Math, Aug. 2000. [3] D. Johns and K. Martin, Analog Integrated Circuit Design. Wiley, Nov. 1996. [4] P. Furth and A. Andreou, "Linearised differential transconductors in subthreshold CMOS," Electronics Letters, vol. 31, no. 7, pp. 545-547, 1995. [5] A. Arnaud and C. Galup-Montoro, "Pico-AN range CMOS transconduc­tors using series-parallel current division," Electronics Letters, vol. 39, no. 18, pp. 1295-1296,2003. [6] Y. Vincence, C. Galup-Montoro, and M. Schneider, "Low-voltage class AB operational amplifier," in Integrated Circuits and Systems Design, 2001, 14th Symposium on., 2001, pp. 207-211. [7] H. de Moura Santos and A. Cunha, "CMOS OTA sizing using ACM model in a graphical approach," in Integrated Circuits and Systems DeSign, 2002. Proceedings. 15th Symposium on, 2002, pp. 289-295. [8] H. D. Dammak, S. Bensalem, S. Zouari, and M. LoulouR, "Design of folded cascode ota in different regions of operation through gm/ID methodology," International Journal of Electrical and Electronics En­gineering, vol. 1, no. 3, pp. 178-183,2008. [9] B. Linares-Barranco and T. Serrano-Gotarredona, "On the design and characterization of femtoampere current-mode circuits," Solid-State Cir­cuits, IEEE Journal of, vol. 38, no. 8, pp. 1353-1363, 2003. [10] J. Ramirez-Angulo, C. Durbha, A. Lopez-Martin, and R. Carvajal, "Highly linear wide tuning range CMOS transconductor operating in moderate inversion," in Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, vol. 1,2004, pp. 1-805-8 YoU. (a) Bandpass filter (875Hz, 437Hz). (b) Bandpass filter (437Hz, 219Hz). (c) Bandpass filter (219Hz, 109Hz). Fig. 8. Frequency response for a three bandpass parallel bank filter implemented with the designed OTAs (two IC's tested). The adjustable bias current of the OTAs allowed for a fine tuning of the cutoff frequencies, to compensate for capacitance and transconductance process deviations. [11] F. Krummenacher and N. Joehl, "A 4-MHz CMOS continuous-time filter with on-chip automatic tuning," Solid-State Circuits, IEEE Journal of, vol. 23, no. 3, pp. 750-758, 1988. [12] C. Enz and E. Vitoz, Designing Low Power Digital Systems: Emerging Technologies. Hindawi, 1996, ch. 1.2 CMOS Low-Power Analog Circuit Design, pp. 79-133. [13] C. Dualibe, "Class notes: Diseno de filtros GmC," 2da Escuela Argentina de Microelectr6nica. C6rdoba. Power Point Presentation., Julio 2007. [14] A. Arnaud, "Very large time constant Gm-C filters," Ph.D. dissertation, Universidad de la Republica, Uruguay, Montevideo, Uruguay, 2002. 163 

A simple approach for the design of operational transconductance amplifiers for low power signal processing

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A simple approach for the design of operational transconductance amplifiers for low power signal processing

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