The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the learning process for industrial engineers in accessing powerful synthesis tools provided for Signal Transition Graphs by sacrificing some of the expressive power of the latter. This formalism is developed based on feedback from engineers of Dialog Semiconductor.Peer ReviewedPostprint (author's final draft

Cortadella, Jordi

Lloyd, David

Moreno Vega, Alberto

Sokolov, Danil

Yakovlev, Alex

English

The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the learning process for industrial engineers in accessing powerful synthesis tools provided for Signal Transition Graphs by sacrificing some of the expressive power of the latter. This formalism is developed based on feedback from engineers of Dialog Semiconductor.Peer Reviewe

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Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours

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Waveform Transition Graphs: A designer-friendlyformalism for asynchronous behavioursJordi Cortadella∗, Alberto Moreno∗, Danil Sokolov†, Alex Yakovlev†, David Lloyd‡∗Universitat Politècnica de Catalunya, Spain; †Newcastle University, UK; ‡Dialog Semiconductor, UKI. INTRODUCTIONThe paper proposes a new formal model for describing asyn-chronous behaviours involving the interplay of causality, concurrencyand choice. The model is called Waveform Transition Graphs. Itsmain aim is simplifying the learning process for industrial engineersin accessing powerful synthesis tools provided for Signal TransitionGraphs by sacrificing some of the expressive power of the latter. Thisformalism is developed based on feedback from engineers of DialogSemiconductor.Asynchronous design is now seen as a promising solution in newapplication areas such as analogue and mixed-signal (AMS) systems.It offers extra value to such systems, going beyond the traditionalscope of pure digital domain, namely better power conversion effi-ciency, lower output ripple, faster response time to analogue events,reduced inductor size and so on [1]. Furthermore, asynchronousdesign, if supported by user-friendly tools, is an attractive optionfor engineers who accept the nature of ‘continuous time’ inherent inasynchronous designs. While the success in applying asynchronouslogic to AMS systems demonstrates the win-win situation for asyn-chronous methodology, the main challenge is currently in making theentry path for the electronic designers easier. Indeed, the availabilityof the Signal Transition Graph (STG) model and powerful modellingand synthesis tools such as PETRIFY [2] and WORKCRAFT [3]facilitates design automation for asynchronous controllers. However,the main stumbling block is concerned with the complexity ofhandling concurrency and choice inherent in STGs, whose underlyingmodel is Petri nets. Most of the electronic designers are not familiarwith Petri nets and the key aspects of modelling concurrency andchoice in them, viz. places, transitions, tokens, conflicts, persistencyetc. Those are typically better understood by computer scientists.We formulate the following requirements for a new behaviouralmodel of circuits for easier adoption by practical engineers:• Powerful expressiveness (maybe a little bit less than the STGs).• Efficient (use logic synthesis, not syntax-directed translation).• Reuse of the existing infrastructure for STGs.• Simple strategies for synthesis and verification (with delays).Addressing the expressiveness, which is the main focus of thispaper, we would like to separate the two major modelling aspects:1) Order of events, i.e. the causality and concurrency relations.2) Choice between different modes of operation, such as forexample read and write modes in interface specifications.We thus forbid concurrency to take place during the states in whichwe have choice and merge between different modes.Regarding aspect (1), the use of signal transition labels and causaldependencies between them in STGs is a good stepping stone. Thisfeature has strong notational connections with signal waveforms,or timing diagrams, the language that practical designers usuallyfeel very comfortable with. Those naturally capture causality andconcurrency and, informally, correspond to the subset of STGs calledMarked Graphs.Regarding aspect (2), the use of places for choice and merge isanother stepping stone for us. It has a strong link with the notion ofstates in finite state machines, which are also familiar to electronicdesigners, both digital and analog. In this work we are proposing tobuild on these links and come up with a new model of WaveformTransition Graphs (WTGs).Examples of related work include the following. With respectto aspect (1), perhaps the most notable was the Waves model andsynthesis method of [4]. The model lacked a path towards generatinga complete synthesizable model of the control circuit behaviour. Itwas targeted at synchronous implementation through the syntax-directsynthesis process, implemented in the JANUS tool, and hence lackedefficiency compared to what is now possible for STGs. With respectto aspect (2), the main reference point would be Burst Mode andeXtended Burst Mode (XBM) automata, supported by the synthesistools MINIMALIST and 3D [5]. The limitation of those for ourpurposes is in the restricted forms in which causality and concurrencywas captured in the transitions between states.II. INTRODUCING WTGS BY MEANS OF AN EXAMPLEFor those familiar with the specification of asynchronous con-trollers, WTGs can be informally described as a subclass of STGs inwhich concurrency and choice are mutually exclusive. From anotherpoint of view, WTGs can also be seen as XBMs [5] in which eacharc represents a WaveForm (WF) (instead of an input/output burst),where a WF is a set of signal events ordered by causality relations.Fig. 1a depicts an example of WTG describing the behaviour of abuck controller [1]. The WTG has two states (s0 and s1) and threeWFs (the three boxes in the diagram). The states in WFs are callednodal states, representing the fact that all the events enabled in thestate were not enabled in the predecessor states.Each WF represents a partial behaviour of the system betweentwo states (entry and exit). The sequencing of WFs is determinedby the arcs connecting states and WFs. State s0 represents a choicebetween two partial behaviours. The selection is done by the firstentry transitions of each WF. After all the events of a WF haveoccurred, the exit state of the WF is activated.Note that WTGs are more expressive than XBMs since they allowinput/output concurrency. However, they are less expressive thanSTGs since no event can be concurrent during a choice.WTGs also allow the specification of unknown behaviour, e.g., itis possible to specify that the value of a signal is unstable betweentwo events. For example, in the WF named later_or_no_zc,the value of signal zc is unstable between the events uv↑ and uv↓(shown as a dashed line in the figure). WTGs can also specify stablesignals with unknown value and Boolean guards for the selection ofWFs during choices (the details are omitted in this paper).Given that WTGs are a subclass of STGs, similar implementabilityconditions apply for the synthesis of speed-independent circuits, i.e.,consistency, persistence and complete state coding [2].Given a WTG, an STG with equivalent behaviour can be derivedby using syntax-directed translation rules. For unstable signals the(a) WTG.(b) Synthesised STG model.Fig. 1: Specification of basic buck controller.translation rules result in more intricate Petri nets structures in whichsilent events and self-loop arcs are also present. Fig. 1b depicts theSTG obtained from the WTG in Fig. 1a where silent events havebeen inserted to delimit the entry and exit transitions of the WFs.The rightmost box of the figure contains the structure that handlesthe instability of signal zc in one fragment of the behaviour.The STG is simply an intermediate form that allows to use existingflows for synthesis and verification. The tangled structures of the STGare not required to be shown to the designer.III. DESIGN EXAMPLESRestrictions imposed by WTGs direct a designer to simpler andcleaner specifications, thus reducing the number of errors and improv-ing productivity. The formalism is still powerful enough to expressa wide range of behaviours using a handful of design strategies.We next discuss a couple of examples that require the use of suchstrategies to fit the WTG model.Occasionally, the initial state may not be a nodal state and cannotbe used for defining cyclic behaviours with WTGs. For example,consider a latch controller specified by the STG in Fig. 2a. Event lr+is enabled in the initial state, but also enabled in some predecessorstate (before firing ra-). This can be modelled by a WTG witha WF that separates the initialisation sequence (start) from thesteady behaviour (repeat), thus leading the system from the initialstate s0 to a nodal state s1, as shown in Fig.2b. Note that thisspecification still cannot be expressed with XBM formalism.(a) STG. (b) WTG.Fig. 2: Specification of latch controller.WTGs do not allow concurrency between conflicting scenarios,which is a limiting factor when exit from one operation mode overlapswith the selection of the next mode, as in VME bus controllerexample, see Fig. 3a. One way around it is to reduce the concurrencyof the system, so there is no such undesired behaviour. In VME buscontroller this can be achieved by delaying dtack- output untilldtack- input is received, as shown by the dotted arc. The WTGspecification of VME bus controller after concurrency reduction isshown in Fig. 3b. When reducing concurrency, care should be takento preserve the protocol with the circuit environment and avoidsignificant performance losses.(a) STG. (b) WTG.Fig. 3: Specification of VME bus controller.IV. DESIGN FLOWThe WTG formalism has been implemented as an interpretedgraph model plugin for WORKCRAFT [3]. It provides a convenientfrontend for editing WTGs and relies on a backend tool WAVER toconvert a WTG specification into an equivalent STG. This enablesthe reuse of the existing design flow for interactive simulation,formal verification, logic synthesis, and technology mapping ofasynchronous controllers.Note: The WTG-based design flow and its CAD tools will bedemonstrated at the conference venue.REFERENCES[1] D. Sokolov et al: “Benefits of asynchronous control for analog elec-tronics: multiphase buck case study”. DATE, 2017.[2] J. Cortadella et al: “Logic synthesis for asynchronous controllers andinterfaces”. Springer-Verlag, 2002.[3] WORKCRAFT homepage. http://www.workcraft.org/.[4] G. Borriello: “A new interface specification methodology and itsapplication to transducer synthesis”. University of California, PhDthesis, 1988.[5] K. Yun, D. Dill, S. Nowick: “Synthesis of 3D asynchronous statemachines”. ICCD, 1992.

Jordi Cortadella

Alberto Moreno

Danil Sokolov

Alex Yakovlev

David Lloyd

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Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours

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Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours

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